📄 1368_1.rpt
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Project Information c:\mev\live\1368\pld\1368_1.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 04/10/2001 19:09:13
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
1368_1 EPM3064ATC100-10 32 27 0 28 0 43 %
User Pins: 32 27 0
Project Information c:\mev\live\1368\pld\1368_1.rpt
** PROJECT COMPILATION MESSAGES **
Warning: GLOBAL primitive on node 'LCLK' feeds logic -- non-global signal usage may result
Warning: Primitive 'PC1' is stuck at GND
Warning: Primitive 'PC8' is stuck at GND
Warning: Primitive 'PC12' is stuck at GND
Warning: Primitive 'PC9' is stuck at GND
Warning: Primitive 'PC11' is stuck at GND
Warning: Primitive 'PC10' is stuck at GND
Warning: Primitive 'PC16' is stuck at GND
Warning: Primitive 'PC13' is stuck at GND
Warning: Primitive 'PC15' is stuck at GND
Warning: Primitive 'PC14' is stuck at GND
Warning: Primitive 'PC20' is stuck at GND
Warning: Primitive 'PC17' is stuck at GND
Warning: Primitive 'PC18' is stuck at GND
Warning: Primitive 'PC19' is stuck at GND
Warning: Primitive 'PC21' is stuck at GND
Project Information c:\mev\live\1368\pld\1368_1.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal '32MHZ' chosen for auto global Clock
INFO: Signal 'LCLK' chosen for auto global Clock
Project Information c:\mev\live\1368\pld\1368_1.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
1368_1@25 ALE
1368_1@12 /CSRAM
1368_1@30 /CSROM
1368_1@31 /CSROMO
1368_1@13 /CS0
1368_1@14 /CS1
1368_1@40 IRQ2/9
1368_1@41 IRQ3
1368_1@42 IRQ4
1368_1@44 IRQ5
1368_1@45 IRQ6
1368_1@46 IRQ7
1368_1@47 IRQ10
1368_1@48 IRQ11
1368_1@52 IRQ12
1368_1@54 IRQ14
1368_1@56 IRQ15
1368_1@57 ISA_INT
1368_1@16 LA20
1368_1@17 LA21
1368_1@19 LA22
1368_1@20 LA23
1368_1@6 /LBE0
1368_1@8 /LBE1
1368_1@9 /LBE2
1368_1@10 /LBE3
1368_1@90 LCLK
1368_1@23 LHOLD
1368_1@21 LHOLDA
1368_1@32 /NOWSI
1368_1@35 /NOWSO
1368_1@29 PC1
1368_1@63 PC8
1368_1@64 PC9
1368_1@67 PC10
1368_1@68 PC11
1368_1@69 PC12
1368_1@71 PC13
1368_1@75 PC14
1368_1@76 PC15
1368_1@79 PC16
1368_1@80 PC17
1368_1@81 PC18
1368_1@83 PC19
1368_1@84 PC20
1368_1@85 PC21
1368_1@92 /RCS0
1368_1@93 /RCS1
1368_1@94 /RCS2
1368_1@96 /RCS3
1368_1@61 /RWE
1368_1@58 /SMEMR
1368_1@60 /SMEMW
1368_1@88 /WR
1368_1@36 /XCSRAM
1368_1@37 /XCSROM
1368_1@99 8MHZ
1368_1@100 16MHZ
1368_1@87 32MHZ
Project Information c:\mev\live\1368\pld\1368_1.rpt
** FILE HIERARCHY **
|9052rdfif:169|
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
***** Logic for device '1368_1' compiled without errors.
Device: EPM3064ATC100-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** ERROR SUMMARY **
Info: Chip '1368_1' in device 'EPM3064ATC100-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R
E E
S S V
1 E E / / / / C 3 V
6 8 R R R R R R C L 2 P P P C P P P N P
M M V V C G C C C I C G / M G C C C C C C C G . C
H H E E S N S S S N L N W H N 2 2 1 I 1 1 1 N C 1
Z Z D D 3 D 2 1 0 T K D R Z D 1 0 9 O 8 7 6 D . 5
----------------------------------------------------_
/ 100 98 96 94 92 90 88 86 84 82 80 78 76 |_
/ 99 97 95 93 91 89 87 85 83 81 79 77 |
N.C. | 1 75 | PC14
N.C. | 2 74 | GND
VCCIO | 3 73 | #TDO
#TDI | 4 72 | N.C.
N.C. | 5 71 | PC13
/LBE0 | 6 70 | N.C.
N.C. | 7 69 | PC12
/LBE1 | 8 68 | PC11
/LBE2 | 9 67 | PC10
/LBE3 | 10 66 | VCCIO
GND | 11 65 | GND
/CSRAM | 12 64 | PC9
/CS0 | 13 EPM3064ATC100-10 63 | PC8
/CS1 | 14 62 | #TCK
#TMS | 15 61 | /RWE
LA20 | 16 60 | /SMEMW
LA21 | 17 59 | GND
VCCIO | 18 58 | /SMEMR
LA22 | 19 57 | ISA_INT
LA23 | 20 56 | IRQ15
LHOLDA | 21 55 | N.C.
N.C. | 22 54 | IRQ14
LHOLD | 23 53 | GND
N.C. | 24 52 | IRQ12
ALE | 25 51 | VCCIO
| 27 29 31 33 35 37 39 41 43 45 47 49 _|
\ 26 28 30 32 34 36 38 40 42 44 46 48 50 |
\-----------------------------------------------------
G N N P / / / G V / / / G V I I I G I I I I I N N
N . . C C C N N C N X X N C R R R N R R R R R . .
D C C 1 S S O D C O C C D C Q Q Q D Q Q Q Q Q C C
. . R R W I W S S I 2 3 4 5 6 7 1 1 . .
O O S O S R R N / 0 1
M M I O A O T 9
O M M
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\mev\live\1368\pld\1368_1.rpt
1368_1
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 6/16( 37%) 14/16( 87%) 0/16( 0%) 8/36( 22%)
B: LC17 - LC32 3/16( 18%) 15/15(100%) 0/16( 0%) 5/36( 13%)
C: LC33 - LC48 4/16( 25%) 16/16(100%) 0/16( 0%) 19/36( 52%)
D: LC49 - LC64 15/16( 93%) 15/15(100%) 0/16( 0%) 2/36( 5%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 60/62 ( 96%)
Total logic cells used: 28/64 ( 43%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 28/64 ( 43%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 1.85
Total fan-in: 52
Total input pins required: 32
Total output pins required: 27
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 28
Total flipflops required: 4
Total product terms required: 36
Total logic cells lending parallel expanders: 0
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