9052rdfif.vhd

用pci9052开发pci板卡的全套资料,含有原理图封装,和eeprom文件1

-- Copyright (C) 1991-2001 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.

-- PROGRAM "Quartus II"
-- VERSION "Version 1.0 Build 112 02/01/2001 SJ"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY \9052rdfif\ IS 
	port
	(
		LCLK :  IN  STD_LOGIC;
		LHOLD :  IN  STD_LOGIC;
		LHOLDA :  IN  STD_LOGIC;
		ALE :  IN  STD_LOGIC;
		IRQ12 :  IN  STD_LOGIC;
		IRQ15 :  IN  STD_LOGIC;
		IRQ14 :  IN  STD_LOGIC;
		IRQ6 :  IN  STD_LOGIC;
		IRQ11 :  IN  STD_LOGIC;
		IRQ10 :  IN  STD_LOGIC;
		IRQ7 :  IN  STD_LOGIC;
		IRQ5 :  IN  STD_LOGIC;
		IRQ4 :  IN  STD_LOGIC;
		IRQ3 :  IN  STD_LOGIC;
		CLK32MHZ :  IN  STD_LOGIC;
		IRQ2TO9 :  IN  STD_LOGIC;
		CS0n :  IN  STD_LOGIC;
		CS1n :  IN  STD_LOGIC;
		NOWSIn :  IN  STD_LOGIC;
		CSRAMn :  IN  STD_LOGIC;
		XCSRAMn :  IN  STD_LOGIC;
		LBE0n :  IN  STD_LOGIC;
		LBE1n :  IN  STD_LOGIC;
		LBE2n :  IN  STD_LOGIC;
		LBE3n :  IN  STD_LOGIC;
		WRn :  IN  STD_LOGIC;
		CSROMn :  IN  STD_LOGIC;
		XCSROMn :  IN  STD_LOGIC;
		LA :  IN  STD_LOGIC_VECTOR(23 downto 20);
		ISA_INT1 :  OUT  STD_LOGIC;
		CLK16MHZ :  OUT  STD_LOGIC;
		CLK8MHZ :  OUT  STD_LOGIC;
		SMEMRn :  OUT  STD_LOGIC;
		SMEMWn :  OUT  STD_LOGIC;
		NOWSOn :  OUT  STD_LOGIC;
		RCS0n :  OUT  STD_LOGIC;
		RCS1n :  OUT  STD_LOGIC;
		RCS2n :  OUT  STD_LOGIC;
		RCS3n :  OUT  STD_LOGIC;
		RWEn :  OUT  STD_LOGIC;
		CSROMOn :  OUT  STD_LOGIC
	);
END \9052rdfif\;

ARCHITECTURE bdf_type OF \9052rdfif\ IS 

signal	LMASTER :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	altera_synthesized_wire_16 :  STD_LOGIC;
signal	altera_synthesized_wire_17 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_14 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_15 :  STD_LOGIC;


BEGIN 
CLK16MHZ <= SYNTHESIZED_WIRE_1;
SYNTHESIZED_WIRE_0 <= '1';
SYNTHESIZED_WIRE_2 <= '0';



altera_synthesized_wire_16 <= LA(23) OR LA(22) OR LA(21) OR LA(20);

process(CLK32MHZ)
variable SYNTHESIZED_WIRE_1_synthesized_var : STD_LOGIC;
begin
if (rising_edge(CLK32MHZ)) then
	SYNTHESIZED_WIRE_1_synthesized_var := SYNTHESIZED_WIRE_1_synthesized_var XOR SYNTHESIZED_WIRE_0;
end if;
	SYNTHESIZED_WIRE_1 <= SYNTHESIZED_WIRE_1_synthesized_var;
end process;

process(CLK32MHZ)
variable CLK8MHZ_synthesized_var : STD_LOGIC;
begin
if (rising_edge(CLK32MHZ)) then
	CLK8MHZ_synthesized_var := CLK8MHZ_synthesized_var XOR SYNTHESIZED_WIRE_1;
end if;
	CLK8MHZ <= CLK8MHZ_synthesized_var;
end process;

ISA_INT1 <= IRQ12 OR IRQ14 OR IRQ15 OR SYNTHESIZED_WIRE_2 OR IRQ11 OR IRQ10 OR IRQ7 OR IRQ6 OR IRQ5 OR IRQ4 OR IRQ3 OR IRQ2TO9;

SMEMRn <= CS0n OR altera_synthesized_wire_16;

SMEMWn <= CS1n OR altera_synthesized_wire_16;

RCS0n <= altera_synthesized_wire_17 OR LBE0n;

RCS1n <= altera_synthesized_wire_17 OR LBE1n;

process(LHOLDA,LHOLD)
begin
if (LHOLD = '0') then
	LMASTER <= '0';
elsif (rising_edge(LHOLDA)) then
	LMASTER <= LHOLD;
end if;
end process;

RCS2n <= altera_synthesized_wire_17 OR LBE2n;

altera_synthesized_wire_17 <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_9;

SYNTHESIZED_WIRE_8 <= CSRAMn OR LMASTER;

SYNTHESIZED_WIRE_9 <= XCSRAMn OR SYNTHESIZED_WIRE_10;

SYNTHESIZED_WIRE_10 <= NOT(LMASTER);


SYNTHESIZED_WIRE_13 <= CSROMn OR LMASTER;

RCS3n <= altera_synthesized_wire_17 OR LBE3n;

SYNTHESIZED_WIRE_14 <= XCSROMn OR SYNTHESIZED_WIRE_12;

CSROMOn <= SYNTHESIZED_WIRE_13 AND SYNTHESIZED_WIRE_14;

SYNTHESIZED_WIRE_12 <= NOT(LMASTER);


process(LCLK,SYNTHESIZED_WIRE_15)
begin
if (SYNTHESIZED_WIRE_15 = '0') then
	NOWSOn <= '1';
elsif (rising_edge(LCLK)) then
	NOWSOn <= NOWSIn;
end if;
end process;

SYNTHESIZED_WIRE_15 <= NOT(ALE);


RWEn <= WRn OR LCLK;

END;