9052rdfif.v

用pci9052开发pci板卡的全套资料,含有原理图封装,和eeprom文件1

// Copyright (C) 1991-2001 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.

module \9052rdfif(
	LCLK,
	LHOLD,
	LHOLDA,
	ALE,
	IRQ12,
	IRQ15,
	IRQ14,
	IRQ6,
	IRQ11,
	IRQ10,
	IRQ7,
	IRQ5,
	IRQ4,
	IRQ3,
	CLK32MHZ,
	IRQ2TO9,
	CS0n,
	CS1n,
	NOWSIn,
	CSRAMn,
	XCSRAMn,
	LBE0n,
	LBE1n,
	LBE2n,
	LBE3n,
	WRn,
	CSROMn,
	XCSROMn,
	LA,
	ISA_INT1,
	CLK16MHZ,
	CLK8MHZ,
	SMEMRn,
	SMEMWn,
	NOWSOn,
	RCS0n,
	RCS1n,
	RCS2n,
	RCS3n,
	RWEn,
	CSROMOn
);

input	LCLK;
input	LHOLD;
input	LHOLDA;
input	ALE;
input	IRQ12;
input	IRQ15;
input	IRQ14;
input	IRQ6;
input	IRQ11;
input	IRQ10;
input	IRQ7;
input	IRQ5;
input	IRQ4;
input	IRQ3;
input	CLK32MHZ;
input	IRQ2TO9;
input	CS0n;
input	CS1n;
input	NOWSIn;
input	CSRAMn;
input	XCSRAMn;
input	LBE0n;
input	LBE1n;
input	LBE2n;
input	LBE3n;
input	WRn;
input	CSROMn;
input	XCSROMn;
input	[23:20] LA;
output	ISA_INT1;
output	CLK16MHZ;
output	CLK8MHZ;
reg	CLK8MHZ;
output	SMEMRn;
output	SMEMWn;
output	NOWSOn;
reg	NOWSOn;
output	RCS0n;
output	RCS1n;
output	RCS2n;
output	RCS3n;
output	RWEn;
output	CSROMOn;

reg	LMASTER;
wire	SYNTHESIZED_WIRE_0;
reg	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_16;
wire	SYNTHESIZED_WIRE_17;
wire	SYNTHESIZED_WIRE_8;
wire	SYNTHESIZED_WIRE_9;
wire	SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_12;
wire	SYNTHESIZED_WIRE_13;
wire	SYNTHESIZED_WIRE_14;
wire	SYNTHESIZED_WIRE_15;

assign	CLK16MHZ = SYNTHESIZED_WIRE_1;
assign	SYNTHESIZED_WIRE_0 = 1;
assign	SYNTHESIZED_WIRE_2 = 0;

assign	SYNTHESIZED_WIRE_16 = LA[23] | LA[22] | LA[21] | LA[20];

always@(posedge CLK32MHZ)
begin
	SYNTHESIZED_WIRE_1 = SYNTHESIZED_WIRE_1 ^ SYNTHESIZED_WIRE_0;
end

always@(posedge CLK32MHZ)
begin
	CLK8MHZ = CLK8MHZ ^ SYNTHESIZED_WIRE_1;
end
assign	ISA_INT1 = IRQ12 | IRQ14 | IRQ15 | SYNTHESIZED_WIRE_2 | IRQ11 | IRQ10 | IRQ7 | IRQ6 | IRQ5 | IRQ4 | IRQ3 | IRQ2TO9;
assign	SMEMRn = CS0n | SYNTHESIZED_WIRE_16;
assign	SMEMWn = CS1n | SYNTHESIZED_WIRE_16;
assign	RCS0n = SYNTHESIZED_WIRE_17 | LBE0n;
assign	RCS1n = SYNTHESIZED_WIRE_17 | LBE1n;

always@(posedge LHOLDA or negedge LHOLD)
begin
if (!LHOLD)
	begin
	LMASTER = 0;
	end
else
	begin
	LMASTER = LHOLD;
	end
end
assign	RCS2n = SYNTHESIZED_WIRE_17 | LBE2n;
assign	SYNTHESIZED_WIRE_17 = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_9;
assign	SYNTHESIZED_WIRE_8 = CSRAMn | LMASTER;
assign	SYNTHESIZED_WIRE_9 = XCSRAMn | SYNTHESIZED_WIRE_10;
assign	SYNTHESIZED_WIRE_10 =  ~LMASTER;
assign	SYNTHESIZED_WIRE_13 = CSROMn | LMASTER;
assign	RCS3n = SYNTHESIZED_WIRE_17 | LBE3n;
assign	SYNTHESIZED_WIRE_14 = XCSROMn | SYNTHESIZED_WIRE_12;
assign	CSROMOn = SYNTHESIZED_WIRE_13 & SYNTHESIZED_WIRE_14;
assign	SYNTHESIZED_WIRE_12 =  ~LMASTER;

always@(posedge LCLK or negedge SYNTHESIZED_WIRE_15)
begin
if (!SYNTHESIZED_WIRE_15)
	begin
	NOWSOn = 1;
	end
else
	begin
	NOWSOn = NOWSIn;
	end
end
assign	SYNTHESIZED_WIRE_15 =  ~ALE;
assign	RWEn = WRn | LCLK;




endmodule