reg764.sfr

高速单片机LPC900系列的C语言头文件。

// Include file for 87C764 SFR Definitions for Tasking C compiler
// Philips Semiconductors. Revision 1.1 05/03/99

_sfrbyte     ACC     _at( 0xE0 )  ;// Accumulator

_sfrbyte     AUXR1   _at( 0xA2 )  ;// Auxiliary Function Register

_sfrbyte     B       _at( 0xF0 )  ;// B Register

_sfrbyte     CMP1    _at( 0xAC )  ;// Comparator 1 Control Register
_sfrbyte     CMP2    _at( 0xAD )  ;// Comparator 2 Control Register

_sfrbyte     DIVM    _at( 0x95 )  ;// CPU Clock Divide-By-M Control

_sfrbyte     DPL     _at( 0x82 )  ;// Data Pointer - Low Byte
_sfrbyte     DPH     _at( 0x83 )  ;// Data Pointer - High Byte

_sfrbyte     I2CFG   _at( 0xC8 )         ;// I2C Configuration Register
_sfrbit      CT0     _atbit( I2CFG, 0 )  ;// Clock Time Select 0
_sfrbit      CT1     _atbit( I2CFG, 1 )  ;// Clock Time Select 1
_sfrbit      TIRUN   _atbit( I2CFG, 4 )  ;// Timer I Run Enable
_sfrbit      CLRTI   _atbit( I2CFG, 5 )  ;// Clear Timer I
_sfrbit      MASTRQ  _atbit( I2CFG, 6 )  ;// Master Request
_sfrbit      SLAVEN  _atbit( I2CFG, 7 )  ;// Slave Enable
                                  
_sfrbyte     I2CON   _at( 0xD8 )         ;// I2C Control Register
_sfrbit      MASTER  _atbit( I2CON, 1 )  ;// Master Status
_sfrbit      STP     _atbit( I2CON, 2 )  ;// Stop Detect Flag
_sfrbit      STR     _atbit( I2CON, 3 )  ;// Start Detect Flag
_sfrbit      ARL     _atbit( I2CON, 4 )  ;// Arbitration Loss Flag
_sfrbit      DRDY    _atbit( I2CON, 5 )  ;// Data Ready Flag
_sfrbit      ATN     _atbit( I2CON, 6 )  ;// Attention: I2C Interrupt Flag
_sfrbit      RDAT    _atbit( I2CON, 7 )  ;// I2C Read Data

_sfrbyte     I2DAT   _at( 0xD9 )  ;// I2C Data Register

_sfrbyte     IEN0    _at( 0xA8 )        ;// Interrupt Enable Register 0
_sfrbit      EX0     _atbit( IEN0, 0 )  ;// External Interrupt 0 Enable
_sfrbit      ET0     _atbit( IEN0, 1 )  ;// Timer 0 Interrupt Enable
_sfrbit      EX1     _atbit( IEN0, 2 )  ;// External Interrupt 1 Enable
_sfrbit      ET1     _atbit( IEN0, 3 )  ;// Timer 1 Interrupt Enable
_sfrbit      ES      _atbit( IEN0, 4 )  ;// Serial Port Interrupt Enable
_sfrbit      EBO     _atbit( IEN0, 5 )  ;// Brownout Interrupt Enable
_sfrbit      EWD     _atbit( IEN0, 6 )  ;// Watchdog Interrupt Enable
_sfrbit      EA      _atbit( IEN0, 7 )  ;// Global Interrupt Enable

_sfrbyte     IEN1     _at( 0xE8 )      ;// Interrupt Enable Register 1
_sfrbit      EI2     _atbit( IEN1, 0 ) ;// I2C Interrupt Enable
_sfrbit      EKB     _atbit( IEN1, 1 ) ;// Keyboard Interrupt Enable
_sfrbit      EC2     _atbit( IEN1, 2 ) ;// Comparator 2 Interrupt Enable
_sfrbit      EC1     _atbit( IEN1, 5 ) ;// Comparator 1 Interrupt Enable
_sfrbit      ETI     _atbit( IEN1, 7 ) ;// Timer I Interrupt Enable

_sfrbyte     IP0     _at( 0xB8 )       ;// Interrupt Priority 0 Low Byte
_sfrbit      PX0     _atbit( IP0, 0 )  ;// External Interrupt 0 Priority
_sfrbit      PT0     _atbit( IP0, 1 )  ;// Timer 0 Interrupt Priority
_sfrbit      PX1     _atbit( IP0, 2 )  ;// External Interrupt 1 Priority
_sfrbit      PT1     _atbit( IP0, 3 )  ;// Timer 1 Interrupt Priority
_sfrbit      PS      _atbit( IP0, 4 )  ;// Serial Port Interrupt Priority
_sfrbit      PBO     _atbit( IP0, 5 )  ;// Brownout Interrupt Priority
_sfrbit      PWD     _atbit( IP0, 6 )  ;// Watchdog Interrupt Priority

_sfrbyte     IP0H    _at( 0xB7 )  ;// Interrupt Priority 0 High Byte

_sfrbyte     IP1     _at( 0xF8 )       ;// Interrupt Priority 1 Low Byte
_sfrbit      PI2     _atbit( IP1, 0 )  ;// I2C Interrupt Priority
_sfrbit      PKB     _atbit( IP1, 1 )  ;// Keyboard Interrupt Priority
_sfrbit      PC2     _atbit( IP1, 2 )  ;// Comparator 2 Interrupt Priority
_sfrbit      PC1     _atbit( IP1, 5 )  ;// Comparator 1 Interrupt Priority
_sfrbit      PTI     _atbit( IP1, 7 )  ;// Timer I Interrupt Priority

_sfrbyte     IP1H    _at( 0xF7)  ;// Interrupt Priority 1 High Byte

_sfrbyte     KBI     _at( 0x86)  ;// Keyboard Interrupt

_sfrbyte     P0      _at( 0x80 )      ;// Port 0
_sfrbit      CMP2O   _atbit( P0, 0 )  ;// Comparator 2 Output
_sfrbit      CIN2B   _atbit( P0, 1 )  ;// Comparator 2 Input B
_sfrbit      CIN2A   _atbit( P0, 2 )  ;// Comparator 2 Input A
_sfrbit      CIN1B   _atbit( P0, 3 )  ;// Comparator 1 Input B
_sfrbit      CIN1A   _atbit( P0, 4 )  ;// Comparator 1 Input A
_sfrbit      CMPREF  _atbit( P0, 5 )  ;// Comparator Reference Input
_sfrbit      CMP1O   _atbit( P0, 6 )  ;// Comparator 1 Output
_sfrbit      T1      _atbit( P0, 7 )  ;// Timer 1 Count Input/Toggle Output
_sfrbit      P0_0    _atbit( P0, 0 )  ;// Port 0, Bit 0
_sfrbit      P0_1    _atbit( P0, 1 )  ;// Port 0, Bit 1
_sfrbit      P0_2    _atbit( P0, 2 )  ;// Port 0, Bit 2
_sfrbit      P0_3    _atbit( P0, 3 )  ;// Port 0, Bit 3
_sfrbit      P0_4    _atbit( P0, 4 )  ;// Port 0, Bit 4
_sfrbit      P0_5    _atbit( P0, 5 )  ;// Port 0, Bit 5
_sfrbit      P0_6    _atbit( P0, 6 )  ;// Port 0, Bit 6
_sfrbit      P0_7    _atbit( P0, 7 )  ;// Port 0, Bit 7
_sfrbyte     P0M1    _at( 0x84 )      ;// P0 Mode Register 1
_sfrbyte     P0M2    _at( 0x85 )      ;// P0 Mode Register 2

_sfrbyte     P1      _at( 0x90 )      ;// Port 1
_sfrbit      TXD     _atbit( P1, 0 )  ;// Serial Port Transmit Output
_sfrbit      RXD     _atbit( P1, 1 )  ;// Serial Port Receive Input
_sfrbit      T0      _atbit( P1, 2 )  ;// Timer 0 Count Input 
_sfrbit      SCL     _atbit( P1, 2 )  ;// I2C Bus Clock Line
_sfrbit      SDA     _atbit( P1, 3 )  ;// I2C Bus Data Line
_sfrbit      INT0    _atbit( P1, 3 )  ;// External Interrupt 0 Input & I2C SDA
_sfrbit      INT1    _atbit( P1, 4 )  ;// External Interrupt 1 Input
_sfrbit      RST     _atbit( P1, 5 )  ;// Reset
_sfrbit      P1_0    _atbit( P1, 0 )  ;// Port 1, Bit 0
_sfrbit      P1_1    _atbit( P1, 1 )  ;// Port 1, Bit 1
_sfrbit      P1_2    _atbit( P1, 2 )  ;// Port 1, Bit 2
_sfrbit      P1_3    _atbit( P1, 3 )  ;// Port 1, Bit 3
_sfrbit      P1_4    _atbit( P1, 4 )  ;// Port 1, Bit 4
_sfrbit      P1_5    _atbit( P1, 5 )  ;// Port 1, Bit 5
_sfrbit      P1_5    _atbit( P1, 6 )  ;// Port 1, Bit 6
_sfrbit      P1_5    _atbit( P1, 7 )  ;// Port 1, Bit 7
_sfrbyte     P1M1    _at( 0x91 )      ;// P1 Mode Register 1
_sfrbyte     P1M2    _at( 0x92 )      ;// P1 Mode Register 2

_sfrbyte     P2      _at( 0xA0 )      ;// Port 2
_sfrbit      X2      _atbit( P2, 0 )  ;// Crystal 2 & Clkout
_sfrbit      X1      _atbit( P2, 1 )  ;// Crystal 1
_sfrbyte     P2M1    _at( 0xA4 )      ;// P2 Mode Register 1
_sfrbyte     P2M2    _at( 0xA5 )      ;// P2 Mode Register 2

_sfrbyte     PCON    _at( 0x87 )    ;// Power Control

_sfrbyte     PSW     _at( 0xD0 )       ;// Program Status Word
_sfrbit      P       _atbit( PSW, 0 )  ;// Accumulator Parity Flag
_sfrbit      F1      _atbit( PSW, 1 )  ;// Flag 1
_sfrbit      OV      _atbit( PSW, 2 )  ;// Overflow Flag
_sfrbit      RS0     _atbit( PSW, 3 )  ;// Register Bank Select 0
_sfrbit      RS1     _atbit( PSW, 4 )  ;// Register Bank Select 1
_sfrbit      F0      _atbit( PSW, 5 )  ;// Flag 0
_sfrbit      AC      _atbit( PSW, 6 )  ;// Auxiliary Carry Flag
_sfrbit      CY      _atbit( PSW, 7 )  ;// Carry Flag

_sfrbyte     PT0AD   _at( 0xF6 )  ;// Port 0 digital Input Disable

_sfrbyte     SCON    _at( 0x98 )        ;// Serial Port Control
_sfrbit      RI      _atbit( SCON, 0 )  ;// Receive Interrupt Flag
_sfrbit      TI      _atbit( SCON, 1 )  ;// Transmit Interrupt Flag
_sfrbit      RB8     _atbit( SCON, 2 )  ;// Receive Bit 8
_sfrbit      TB8     _atbit( SCON, 3 )  ;// Transmit Bit 8
_sfrbit      REN     _atbit( SCON, 4 )  ;// Receiver Enable
_sfrbit      SM2     _atbit( SCON, 5 )  ;// Serial Mode Control Bit 2
_sfrbit      SM1     _atbit( SCON, 6 )  ;// Serial Mode Control Bit 1
_sfrbit      SM0     _atbit( SCON, 7 )  ;// Serial Mode Control Bit 0
_sfrbyte     SBUF    _at( 0x99 )        ;// Serial Port Buffer
_sfrbyte     SADDR   _at( 0xA9 )        ;// Serial Port Address
_sfrbyte     SADEN   _at( 0xB9 )        ;// Serial Port Address Enable

_sfrbyte     SP      _at( 0x81 )  ;// Stack Pointer

_sfrbyte     TCON    _at( 0x88 )        ;// Timer Control
_sfrbit      IT0     _atbit( TCON, 0 )  ;// External Interrupt 0 Type
_sfrbit      IE0     _atbit( TCON, 1 )  ;// External Interrupt 0 Edge Flag
_sfrbit      IT1     _atbit( TCON, 2 )  ;// External Interrupt 1 Type
_sfrbit      IE1     _atbit( TCON, 3 )  ;// External Interrupt 1 Edge Flag
_sfrbit      TR0     _atbit( TCON, 4 )  ;// Timer 0 Run Control
_sfrbit      TF0     _atbit( TCON, 5 )  ;// Timer 0 Overflow Flag
_sfrbit      TR1     _atbit( TCON, 6 )  ;// Timer 1 Run Control
_sfrbit      TF1     _atbit( TCON, 7 )  ;// Timer 1 Overflow Flag
_sfrbyte     TMOD    _at( 0x89 )        ;// Timer 0 and 1 Mode
_sfrbyte     TH0     _at( 0x8C )        ;// Timer 0 - High Byte
_sfrbyte     TL0     _at( 0x8A )        ;// Timer 0 - Low Byte
_sfrbyte     TH1     _at( 0x8D )        ;// Timer 1 - High Byte
_sfrbyte     TL1     _at( 0x8B )        ;// Timer 1 - Low Byte

_sfrbyte     WDCON   _at( 0xA7 )  ;// Watchdog Control Register
_sfrbyte     WDRST   _at( 0xA6 )  ;// Watchdog Reset (Feed) Register

// End of 87C76x SFR definitions.