fet140_tb_pwm08.s43

基于IAR Workbench for MSP430 的汇编语言例程

;******************************************************************************
;   MSP-FET430P140 Demo - Timer_B PWM TB1-6 up-down mode, XT2 HF XTAL SMCLK
;
;   Description; This program will generate six PWM outputs on P4.x using
;   Timer_B in up-down mode.  The value in CCR0, 512, defines the period/2 
;   and the values in CCRx the duty PWM cycles.  
;   ACLK = n/a, MCLK = SMCLK = TBCLK = XT2 = HF XTAL 
;   //*External watch crystal installed on XT2IN XT2OUT is required for SMCLK*//	  
;
;                MSP430F149
;             -----------------
;         /|\|            XT2IN|-  
;          | |                 | HF XTAL (455k - 8Mhz) 
;          --|RST        XT2OUT|-
;            |                 |
;            |             P4.1|--> CCR1 - 75% PWM
;            |             P4.2|--> CCR2 - 25% PWM
;            |             P4.3|--> CCR3 - 12.5% PWM
;            |             P4.4|--> CCR4 - 6.25% PWM
;            |             P4.5|--> CCR5 - 3.125% PWM
;            |             P4.6|--> CCR6 - 1.5625% PWM
;
;   M.Buccini
;   Texas Instruments, Inc
;   June 2004
;******************************************************************************
#include  "msp430x14x.h"
;------------------------------------------------------------------------------ 
            ORG     01100h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #0A00h,SP               ; Initialize 'x1x9 stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupBC     bic.b   #XT2OFF,&BCSCTL1        ; XT2on
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag 
            mov.w   #0FFh,R15               ; R15 = Delay 
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start 
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set? 
            jnz     SetupOsc                ; OSC Fault, clear flag again 
            bis.b   #SELM_2+SELS,BCSCTL2    ; MCLK = SMCLK = XT2
SetupP4     bis.b   #007Eh,&P4DIR           ; P4.1-P4.6 output
            bis.b   #007Eh,&P4SEL           ; P4.1-P4.6 TB1-62 otions
SetupC0     mov.w   #512-1,&TBCCR0          ; PWM Period 
SetupC1     mov.w   #OUTMOD_2,&TBCCTL1      ; CCR1 toggle/reset
            mov.w   #384,&TBCCR1            ; CCR1 PWM Duty Cycle	  
SetupC2     mov.w   #OUTMOD_2,&TBCCTL2      ; CCR2 toggle/reset
            mov.w   #128,&TBCCR2            ; CCR2 PWM duty cycle	  
SetupC3     mov.w   #OUTMOD_2,&TBCCTL3      ; CCR3 toggle/reset
            mov.w   #64,&TBCCR3             ; CCR3 PWM duty cycle	  
SetupC4     mov.w   #OUTMOD_2,&TBCCTL4      ; CCR4 toggle/reset
            mov.w   #32,&TBCCR4             ; CCR4 PWM duty cycle	  
SetupC5     mov.w   #OUTMOD_2,&TBCCTL5      ; CCR5 toggle/reset
            mov.w   #16,&TBCCR5             ; CCR5 PWM duty cycle	  
SetupC6     mov.w   #OUTMOD_2,&TBCCTL6      ; CCR6 toggle/reset
            mov.w   #8,&TBCCR6              ; CCR6 PWM duty cycle	  
SetupTB     mov.w   #TBSSEL_2+MC_3,&TBCTL   ; SMCLK, up-down mode
                                            ;					  
Mainloop    bis.w   #CPUOFF,SR              ; CPU off
            nop                             ; Required only for debugger
                                            ;
;------------------------------------------------------------------------------ 
;           Interrupt Vectors Used MSP430x13x/14x/15x/16x         
;------------------------------------------------------------------------------ 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            END