fet140_tb06.s43

来自「基于IAR Workbench for MSP430 的汇编语言例程」· S43 代码 · 共 63 行

;******************************************************************************
;   MSP-FET430P140 Demo - Timer_B Toggle P1.0, CCR1 Contmode ISR, DCO SMCLK
;
;   Description; Toggle P1.0 using software and TB_1 ISR. Toggle rate is 
;   set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TBCLK. 
;   Durring the TB_0 ISR P1.0 is toggled and 50000 clock cycles are added to 
;   CCR0.  TB_1 ISR is triggered exactly 50000 cycles. CPU is normally off and
;   used only durring TB_ISR. 
;   MCLK = SMCLK = TBCLK = DCO ~ 800k 
;   Proper use of TBIV interrupt vector generator demonstrated.    
;
;                MSP430F149
;             -----------------
;         /|\|              XIN|-  
;          | |                 |
;          --|RST          XOUT|-
;            |                 |
;            |             P1.0|-->LED
;
;   M.Buccini
;   Texas Instruments, Inc
;   June 2004
;******************************************************************************
#include  "msp430x14x.h"
;----------------------------------------------------------------------------- 
            ORG     01100h                  ; Program Start
;----------------------------------------------------------------------------- 
RESET       mov.w   #0A00h,SP               ; Initialize 'x1x9 stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupP1     bis.b   #001h,&P1DIR            ; P1.0 output 
SetupC1     mov.w   #CCIE,&TBCCTL1          ; CCR1 interrupt enabled
            mov.w   #50000,&TBCCR1          ; 
SetupTA     mov.w   #TBSSEL_2+MC_2,&TBCTL   ; SMCLK, contmode
                                            ;						  
Mainloop    bis.w   #CPUOFF+GIE,SR          ; CPU off, interrupts enabled
            nop                             ; Required for debugger
                                            ;
;------------------------------------------------------------------------------ 
TBX_ISR;    Common ISR for TBCCR1-6 and overflow
;------------------------------------------------------------------------------ 
            add.w   &TBIV,PC                ; Add Timer_B offset vector
            reti                            ; TBCCR0 - no source
            jmp     TBCCR1_ISR              ; TBCCR1
            reti                            ; TBCCR2
            reti                            ; TBCCR3
            reti                            ; TBCCR4
            reti                            ; TBCCR5
            reti                            ; TBCCR6
TB_over     reti                            ; Return from overflow ISR		 
                                            ;
TBCCR1_ISR  add.w   #50000,&TBCCR1          ; Offset until next interrupt
            xor.b   #001h,&P1OUT            ; Toggle P1.0
            reti                            ; Return from overflow ISR		 
                                            ;            
;----------------------------------------------------------------------------- 
;           Interrupt Vectors Used MSP430x13x/14x/15x/16x         
;----------------------------------------------------------------------------- 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            ORG     0FFF8h                  ; Timer_BX Vector
            DW      TBX_ISR                 ; 
            END