fet140_tb_pwm03.s43

来自「基于IAR Workbench for MSP430 的汇编语言例程」· S43 代码 · 共 56 行

;******************************************************************************
;   MSP-FET430P140 Demo - Timer_A PWM TB1-2 upmode, HF XTAL ACLK
;
;   Description; This program will generate two PWM outputs on P4.1/4.2 using
;   Timer_B in upmode.  The value in CCR0, 512, defines the period and the 
;   values in CCR1 and CCR1 the duty PWM cycles.  Using HF XTAL ACLK as TBCLK,
;   the timer period is HF XTAL/512 with a 75% duty cycle on P4.1 and 25% on P4.2. 
;   ACLK = MCLK = TBCLK = HF XTAL
;   //** HF XTAL REQUIRED AND NOT INSTALLED ON FET **//
;
;                MSP430F149
;             -----------------
;         /|\|              XIN|-  
;          | |                 | HF XTAL (455k - 8Mhz) 
;          --|RST          XOUT|-
;            |                 |
;            |             P4.1|--> CCR1 - 75% PWM
;            |             P4.2|--> CCR2 - 25% PWM
;
;   M.Buccini
;   Texas Instruments, Inc
;   June 2004
;******************************************************************************
#include  "msp430x14x.h"
;------------------------------------------------------------------------------ 
            ORG     01100h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #0A00h,SP               ; Initialize 'x1x9 stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupP4     bis.b   #006h,&P4DIR            ; P4.1 and P4.2 output
            bis.b   #006h,&P4SEL            ; P4.1 and P4.2 TB1/2 otions
SetupBC     bis.b   #XTS,&BCSCTL1           ; LFXT1 = HF XTAL
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag 
            mov.w   #0FFh,R15               ; R15 = Delay 
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start 
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set? 
            jnz     SetupOsc                ; OSC Fault, clear flag again 
            bis.b   #SELM_3,&BCSCTL2        ; MCLK = LFXT1
SetupC0     mov.w   #512-1,&TBCCR0          ; PWM Period 
SetupC1     mov.w   #OUTMOD_7,&TBCCTL1      ; CCR1 reset/set
            mov.w   #384,&TBCCR1            ; CCR1 PWM Duty Cycle	  
SetupC2     mov.w   #OUTMOD_7,&TBCCTL2      ; CCR2 reset/set
            mov.w   #128,&TBCCR2            ; CCR2 PWM duty cycle	  
SetupTB     mov.w   #TBSSEL_1+MC_1,&TBCTL   ; ACLK, upmode
                                            ;					  
Mainloop    bis.w   #CPUOFF,SR              ; CPU off
            nop                             ; Required only for debugger
                                            ;
;------------------------------------------------------------------------------ 
;           Interrupt Vectors Used MSP430x13x/14x/15x/16x         
;------------------------------------------------------------------------------ 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            END