fet140_ta09.s43

基于IAR Workbench for MSP430 的汇编语言例程

;******************************************************************************
;   MSP-FET430P140 Demo - Timer_A Toggle P1.0-3 CCRx Contmode ISR, HF XTAL ACLK 
;
;   Description; Use timer_A CCRx units and overflow to generate four
;   independent timing intervals. For demonstration, CCR0, CCR1 and CCR2 output
;   units are optionally selected with port pins P1.1, P1.2 and P1.3 in toggle
;   mode. As such, these pins will toggle when respective CCRx registers match
;   the TAR counter. Interrupts are also enabled with all CCRx units,
;   software loads offset to next inderval only - as long as the interval offset
;   is aded to CCRx, toggle rate is generated in hardware. Timer_A overflow ISR 
;   is used to toggle P1.0 with software. 
;   ACLK = MCLK = TACLK = LFXT1 = HF XTAL
;   As coded with TACLK = HF XTAL and assuming HF XTAL = 8Mhz, toggle rates:
;   P1.1 = CCR0 = 8MHz/(2*200) = 20kHz
;   P1.2 = CCR1 = 8MHz/(2*1000) = 4kHz
;   P1.3 = CCR2 = 8MHz/(2*10000) = 400Hz
;   P1.0 = overflow = 8MHz/(2*65536) = 61Hz
;   Proper use of TAIV interrupt vector generator demonstrated.   
;   //** HF XTAL NOT INSTALLED ON FET **//;
;
;                MSP430F149
;             -----------------
;         /|\|              XIN|-  
;          | |                 | HF XTAL (455k - 8Mhz)
;          --|RST          XOUT|-
;            |                 |
;            |             P1.1|--> CCR0
;            |             P1.2|--> CCR1
;            |             P1.3|--> CCR2
;            |             P1.0|--> overflow/software
;
;   M.Buccini
;   Texas Instruments, Inc
;   January 2004
;******************************************************************************
#include  "msp430x14x.h"
;------------------------------------------------------------------------------ 
            ORG     01100h                  ; Program Start
;------------------------------------------------------------------------------ 
RESET       mov.w   #0A00h,SP               ; Initialize 'x1x9 stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop WDT
SetupP1     bis.b   #00Eh,&P1SEL            ; P1.1 - P1.3 option select
            bis.b   #00Fh,&P1DIR            ; P1.0-3 outputs 
SetupBC     bis.b   #XTS,&BCSCTL1           ; LFXT1 = HF XTAL
SetupOsc    bic.b   #OFIFG,&IFG1            ; Clear OSC fault flag 
            mov.w   #0FFh,R15               ; R15 = Delay 
SetupOsc1   dec.w   R15                     ; Additional delay to ensure start 
            jnz     SetupOsc1               ;
            bit.b   #OFIFG,&IFG1            ; OSC fault flag set? 
            jnz     SetupOsc                ; OSC Fault, clear flag again 
            bis.b   #SELM_3,&BCSCTL2        ; MCLK= LFXT1
SetupC0     mov.w   #OUTMOD_4+CCIE,&CCTL0   ; CCR0 toggle, interrupt enabled
SetupC1     mov.w   #OUTMOD_4+CCIE,&CCTL1   ; CCR1 toggle, interrupt enabled
SetupC2     mov.w   #OUTMOD_4+CCIE,&CCTL2   ; CCR2 toggle, interrupt enabled
SetupTA     mov.w   #TASSEL_1+MC_2+TAIE,&TACTL   ; ACLK, contmode, interrupt
                                            ;													  
Mainloop    bis.w   #CPUOFF+GIE,SR          ; Enter LPM3, interrupts enabled
            nop                             ; Required for debugger
                                            ;
;------------------------------------------------------------------------------ 
TA0_ISR;   
;------------------------------------------------------------------------------ 
            add.w   #200,&CCR0              ; Offset until next interrupt
            reti                            ;		 
                                            ;
;------------------------------------------------------------------------------ 
TAX_ISR;    Common ISR for CCR1-4 and overflow
;------------------------------------------------------------------------------ 
            add.w   &TAIV,PC                ; Add Timer_A offset vector
            reti                            ; CCR0 - no source
            jmp     CCR1_ISR                ; CCR1
            jmp     CCR2_ISR                ; CCR1
            reti                            ; CCR3
            reti                            ; CCR4
TA_over     xor.b   #001h,&P1OUT            ; Toggle P1.0
            reti                            ; Return from overflow ISR		 
                                            ;
CCR1_ISR    add.w   #1000,&CCR1             ; Offset until next interrupt
            reti                            ; Return ISR		 
                                            ;            
CCR2_ISR    add.w   #10000,&CCR2            ; Offset until next interrupt
            reti                            ; Return ISR		 
                                            ;
;----------------------------------------------------------------------------- 
;           Interrupt Vectors Used MSP430x13x/14x/15x/16x         
;----------------------------------------------------------------------------- 
            ORG     0FFFEh                  ; MSP430 RESET Vector
            DW      RESET                   ; 
            ORG     0FFECh                  ; Timer_A0 Vector
            DW      TA0_ISR                 ; 
            ORG     0FFEAh                  ; Timer_AX Vector
            DW      TAX_ISR                 ; 
            END