fet140_tb_pwm02.c

基于IAR Workbench for MSP430 的MSP430c语言例程,

//*******************************************************************************
//  MSP-FET430P140 Demo - Timer_B PWM TB1-6 upmode, 32kHz ACLK
//
//  Description; This program will generate six PWM outputs on P4.x using
//  Timer_B in upmode.  The value in CCR0, defines the period and the 
//  values in CCRx the duty PWM cycles.  Using 32kHz ACLK as TBCLK,
//  the timer period is 15.6ms. 
//  ACLK = TBCLK = LFXT1 = 32768, MCLK = SMCLK = default DCO ~ 800kHz. 
//  Normal mode LPM3
//  //*External watch crystal installed on XIN XOUT is required for ACLK*//	  
//
//               MSP430F149
//            -----------------
//        /|\|              XIN|-  
//         | |                 | 32k
//         --|RST          XOUT|-
//           |                 |
//           |             P4.1|--> CCR1 - 75% PWM
//           |             P4.2|--> CCR2 - 25% PWM
//           |             P4.3|--> CCR3 - 12.5% PWM
//           |             P4.4|--> CCR4 - 6.25% PWM
//           |             P4.5|--> CCR5 - 3.125% PWM
//           |             P4.6|--> CCR6 - 1.5625% PWM
//
//  M.Buccini
//  Texas Instruments, Inc
//  September 2003
//  Built with IAR Embedded Workbench Version: 1.26B
//  June 2004
//  Updated for IAR Embedded Workbench Version: 2.21B
//******************************************************************************

#include <msp430x14x.h>

void main(void)
{ 
  WDTCTL = WDTPW + WDTHOLD;             // Stop WDT
  P4DIR |= 0x7e;                        // P4.1 - P4.6 output
  P4SEL |= 0x7e;                        // P4.1 - P4.6 TBx options
  TBCCR0 = 512-1;                       // PWM Period
  TBCCTL1 = OUTMOD_7;                   // CCR1 reset/set
  TBCCR1 = 384;                         // CCR1 PWM duty cycle
  TBCCTL2 = OUTMOD_7;                   
  TBCCR2 = 128;                         
  TBCCTL3 = OUTMOD_7;                   
  TBCCR3 = 64;                         
  TBCCTL4 = OUTMOD_7;                   
  TBCCR4 = 32;                         
  TBCCTL5 = OUTMOD_7;                   
  TBCCR5 = 16;                         
  TBCCTL6 = OUTMOD_7;                   
  TBCCR6 = 8;                         

  TBCTL = TBSSEL_1 + MC_1;              // ACLK, up mode
  
  _BIS_SR(LPM3_bits);                   // Enter LPM3
}