📄 pq27e_init.c
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/****************************************************************
FILE
$RCSfile: pq27e_init.c,v $
$Date: 2004/10/05 08:25:13 $
$Revision: 1.5 $
DESCRIPTION
MPC8272 ADS initialization file
COPYRIGHT
(c) 2003 Metrowerks Corporation
All rights reserved.
HISTORY
$Log: pq27e_init.c,v $
Revision 1.5 2004/10/05 08:25:13 c-dnegrea
modified to support Cache ISR Debug target
Revision 1.4 2003/11/03 13:39:20 milies
added internal memory configuration for Security Co-Processor (SEC)
******************************************************************/
//----------------------------------------------------------------------------
// Register Offset Definitions. All these values are offsets from the
// Internal Memory Map Register (IMMR) base pointer + 0x10000. The base value
// is determined by the ISB bits in the Hard Reset Configuration Word. See the
// reset section of the user's manual. This list does not comprise all possible
// Internal Memory Mapped Registers.
//----------------------------------------------------------------------------
#define SIUMCR 0x00000000 // SIU Module Configuration Register
#define SYPCR 0x00000004 // System Protection Control Register
#define RMR 0x00000C94 // Reset Mode Register
#define BCR 0x00000024 // Bus Configuration Register
#define PPC_ACR 0x00000028 // 60x Bus Arbiter Configuration Register
#define PPC_ALRH 0x0000002C // 60x Bus Arbitration-Level[High] Register
#define TESCR1 0x00000040 // 60x Bus Transfer Error Status and
// Control Register 1
#define TESCR2 0x00000044 // 60x Bus Transfer Error Status and
// Control Register 2
#define LTESCR1 0x00000048 // Local Bus Transfer Error Status and
// Control Register 1
#define LTESCR2 0x0000004C // Local Bus Transfer Error Status and
// Control Register 2
#define SCCR 0x00000C80 // System Clock Control Register
#define BR0 0x00000100 // Base Register Bank 0
#define OR0 0x00000104 // Option Register Bank 0
#define BR1 0x00000108 // Base Register Bank 1
#define OR1 0x0000010C // Option Register Bank 1
#define BR2 0x00000110 // Base Register Bank 2
#define OR2 0x00000114 // Option Regiser Bank 2
#define BR3 0x00000118 // Base Register Bank 3
#define OR3 0x0000011C // Option Register Bank 3
#define BR4 0x00000120 // Base Register Bank 4
#define OR4 0x00000124 // Option Register Bank 4
#define BR5 0x00000128 // Base Register Bank 5
#define OR5 0x0000012C // Option Register Bank 5
#define BR8 0x00000140 // Base Register Bank 8
#define OR8 0x00000144 // Option Register Bank 8
#define MPTPR 0x00000184 // Memory Periodic Timer Prescaler Register
#define PSDMR 0x00000190 // PowerPC Bus SDRAM Machine Mode Register
#define LSDMR 0x00000194 // Local Bus SDRAM Machine Mode Register
#define PURT 0x00000198 // 60x Bus Assigned UPM Refresh Timer
#define PSRT 0x0000019C // 60x Bus Assigned SDRAM Refresh Timer
#define LURT 0x000001A0 // Local Bus Assigned UPM Refresh Timer
#define LSRT 0x000001A4 // Local Bus Assigned SDRAM Refresh Timer
#define IMMR 0x000001A8 // Internal I/O base register offset
#define PCI_GCR 0x00000880 // PCI General Control Register
#define PCIBR0 0x000001AC // PCI Base Register 0
#define PCIBR1 0x000001B0 // PCI Base Register 1
#define PCIMSK0 0x000001C4 // PCI Mask Register 0
#define PCIMSK1 0x000001C8 // PCI Mask Register 1
#define SECMR 0x000001BC // SEC Mask Register
#define SECBR 0x000001B4 // SEC Base Register
#pragma section code_type ".init"
#ifdef __cplusplus
extern "C" {
#endif
asm void __reset(void);
asm void usr_init();
extern void __start();
extern unsigned long gInterruptVectorTable;
extern unsigned long gInterruptVectorTableEnd;
extern void mmu_cache_init();
#ifdef __cplusplus
}
#endif
asm void __reset(void)
{
//
// Enable machine check exceptions
//
lis r3, 0
ori r3, r3, 0x1002
mtmsr r3
b __start
}
asm void usr_init()
{
nofralloc
//----------------------------------------------
// Load the IMMR register with the base address
//----------------------------------------------
#ifdef ROM_VERSION
addis r4,0,0x0471 // IMMR base addr = 0x04700000+10000. We add
// 0x10000 because using relative addressing
// in load and store instructions only allow a
// offset from the base of +/-32767.
addis r5,0,0x0470
addis r3,0,0x0F01
stw r5,IMMR(r3) // The default IMMR base address was 0x0F0000000 as
// originally programmed into the Hard Reset
// Configuration Word.
mtspr 311,r5
//*******************************************
// Main System Clock Configuration Registers
//*******************************************
//-------------------------------------------------------------------------
// We only need to program the System Clock Control Register (SCCR). The
// System Clock Mode Register (SCMR) doesn't need to be programmed here
// because the MODCLK_HI bits in the Hard Reset Configuration Word and the
// MODCK pins dictate the values in the SCCR during power-on reset.
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Program the System Clock Control Register (SCCR).
//
// - Bits 0 - 22 Reserved. Clear to 0.
//
// - PCI_Mode = 0 (Disabled)
//
// - CLPD (CPM Low Power Disable) = 0 =
//
// CPM does not enter low power mode when the core enters low power
// mode.
//
// - DFBRG (Division Factor of BRGCLK) = 01 - Divide by 8.
//
//-------------------------------------------------------------------------
addis r3,0,0x0000
ori r3,r3,0x0001 // SCCR = 0x00000001
stw r3,SCCR(r4)
//~~~~~~~~~~~~~~~~~~~~
// Initialize the SIU
//~~~~~~~~~~~~~~~~~~~~
//-----------------------------------------------------------------------
// Program the System Protection Control Register with the following
// values:
//
// - SWTC (Software Watchdog Timer Count) = 0xFFFF = programmed to max
// count value.
// - BMT (Bus Monitor Timing) = 0xFF = Set to max timeout period.
// - PBME (60x Bus Monitor Enable) = 1 = enabled.
// - LBME (Local Bus Monitor Enable) = 1 = enabled.
// - Bits 26-28 Reserved. Set to 0.
// - SWE (Software Watchdog Enabled) = 0 = disabled for now. User will
// have to enable this in a non-debug application.
// - SWRI (Software Watchdog Reset/Interrupt Select) = 1 = Software
// watchdog timeout or bus monitor time-out causes a soft reset.
// - SWP (Software Watchdog Prescale) = 1 = clock is prescaled.
//-----------------------------------------------------------------------
addis r3,0,0xFFFF
ori r3,r3,0xFFC3 // SYPCR = 0xFFFFFFC3
stw r3,SYPCR(r4)
addis r3,0,0x0001
stw r3,RMR(r4)
//-------------------------------------------------------------------------
// Program the Bus Configuration Register. The details are as follows:
//
// - EBM (External Bus Mode) = 0 = Single bus mode is assumed.
// - APD (Address Phase delay) = 001 =
// One address tenure wait states for address operations initiated by
// a 60x bus master.
// - L2C (Secondary Cache Controller) = 0 = No secondary cache controller
// is assumed.
// - L2D (L2 cache hit Delay) = 000 = This is a don't care because we're
// not using the L2 cache.
// - PLDP (PipeLine maximum Depth) = 0 = The pipeline max depth is one.
// - EAV (Enable address visibility) = 0 = Bank select signals are driven on 60x bus address lines.
// There is no full address visibility.
// - Bits 10-11 = Reserved. Set to 0.
// - ETM (Compatibility Mode enable) = 1 = Extended transfer mode is
// enabled.
// - LETM (Local Bus Compatibility Mode Enable) = 1 =
// Extended transfer mode is enabled on the local bus.
// - EPAR (Even Parity) = 0 = This is a don't care.
// - LEPAR (Local Bus Even Parity) = 0 = This is a don't care.
// - Bits 16-20 = Reserved. Set to 0.
// - EXDD (External Master Delay Disable) = 0 =
// The memroy controller inserts one wait state between the assertion
// of TS and the assertion of CS when an external master accesses an
// address space controlled by the memory controller.
// - Bits 22-26 = Reserved. Set to 0.
// - ISPS (Internal Space Port Size) = 0 =
// MPC8260 acts as a 64-bit slave to external master accesses to it's
// internal space.
// - Bits 28-31 = Reserved. Set to 0.
//-------------------------------------------------------------------------
addis r3,0,0x100c
stw r3,BCR(r4)
//-------------------------------------------------------------------------
// Program the 60x Bus Arbiter Configuration Register. The details are as
// follows:
//
// - Bits 0-1 = Reserved. Set to 0.
// - DBGD (Data Bus Grant Delay) = Minimum of zero wait states for PowerPC
// master-initiated data operations. This
// is the minimum delay between TS/ and
// DBG/.
// - EARB (External arbitration) = 0 = Internal arbitration is performed
// - PRKM (Parking Master) = 0010 = CPM is at a low request level for the
// parked master.
//-------------------------------------------------------------------------
addi r3,0,0x0002
stb r3,PPC_ACR(r4)
//-------------------------------------------------------------------------
// Program the 60x Bus Arbitration-Level[High] Register. The priority for
// potential bus masters are defined by locating the value associated with
// a particular master from the PRKM field in the PPC_ACR register and
// inserting it's value in the priority field. Priority field 0 is the
// highest priority and the lowest is Priority field 15 in the PPC_ALRH
// register.
//
// - Priority Field 0 = 0000 = CPM high request level
// - Priority Field 1 = 0001 = CPM middle request level
// - Priority Field 2 = 0010 = CPM low request level
// - Priority Field 3 = 0110 = Internal Core
// - Priority Field 4 = 0111 = External Master 1
// - Priority Field 5 = 1000 = External Master 2
// - Priority Field 6 = 1001 = External Master 3
// - Priority Field 7 = 0011 = Reserved
//-------------------------------------------------------------------------
addis r3,0,0x0126
ori r3,r3,0x7893
stw r3,PPC_ALRH(r4)
//--------------------------------------------------------------------------
// Program the 60x Bus Transfer Error Status and Control Register 1. The
// details are as follows:
//
// - DMD (Data Errors Disable) = 1 =
// Disable all data errors on the 60x bus. Also parity single and double
// ECC error.
// - All other bits are either status or reserved bits. All reserved bits
// should be set to 0.
//--------------------------------------------------------------------------
addis r3,0,0x0000
ori r3,r3,0x4000
stw r3,TESCR1(r4)
//--------------------------------------------------------------------------
// Program the 60x Bus Transfer Error Status and Control Register 2.
//--------------------------------------------------------------------------
addis r3,0,0x0000
ori r3,r3,0x0000
stw r3,TESCR2(r4)
//-------------------------------------------------------------------------
// First, program the Memory Periodic Timer Prescaler Register (MPTPR).
// Finding the value to this ties in with the desired SDRAM Refresh
// Timer (PSRT) value and the required Refresh Command interval for
// refreshing each row. The Refresh Command interval is found by
// determining the number of rows on the SDRAM device.
//
// Divide bus clock by 41 (decimal) which is MPTPR+1
//-------------------------------------------------------------------------
addi r5,0,0x2800 //
sth r5,MPTPR(r4) // store half word - bits[16-31]
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Initialize flash
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//-------------------------------------------------------------------------
// Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
// flash that resides on the 8266ADS-PCI board.
// The particulars are defined here.
// BA (Base Address) = 0xFF80+0b for a total of 17 address bits. This value
// represents the upper 17 bits of the base address.
// Bits 17-18 reserved. = 00
// PS (Port Size) = 11b = 32 bit port size
// DECC (Data Error Correction and Checking) = 00 = Data errors checking
// Disabled.
// WP (Write Protect) = 0 = both read and write accesses are allowed
// MS (Machine Select) = 000 = General Purpose Chip Select Machine (GPCM)
// for 60x bus Selected
// EMEMC (External Memory Controller Enable) = 0 = Accesses are handled by
// the memory controller
// according to MSEL.
// ATOM (Atomic Operation) = 00 = The address space controlled by the
// memory controller bank is not used for
// atomic operations.
// DR (Delayed Read) = 0 = Normal operation.
// V (Valid Bit) = 1 = Valid bit set
//-------------------------------------------------------------------------
addis r3,0,0xFF80 // R3 holds the value temporarily
ori r3,r3,0x1801
//-------------------------------------------------------------------------
// Option Register 0 (OR0) for GPCM use: further flash definitions
//
// 8MBbyte block size
// CS early negate,
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