init_mmu_cache.c

mpc2872系列的usb controller产生sof源码

		mtspr  ibat3u, r3
		isync


   // 	setup_dbats
		addis  r0, r0, 0x0000
		addis  r4, r0, DBAT0L_VAL@h
		ori    r4, r4, DBAT0L_VAL@l
		addis  r3, r0, DBAT0U_VAL@h
		ori    r3, r3, DBAT0U_VAL@l
		mtspr  dbat0l, r4
		mtspr  dbat0u, r3
		isync
		
		addis  r4, r0, DBAT1L_VAL@h
		ori    r4, r4, DBAT1L_VAL@l
		addis  r3, r0, DBAT1U_VAL@h
		ori    r3, r3, DBAT1U_VAL@l
		mtspr  dbat1l, r4
		mtspr  dbat1u, r3
		isync
		
		addis  r4, r0, DBAT2L_VAL@h
		ori    r4, r4, DBAT2L_VAL@l
		addis  r3, r0, DBAT2U_VAL@h
		ori    r3, r3, DBAT2U_VAL@l
		mtspr  dbat2l, r4
		mtspr  dbat2u, r3
		isync

		addis  r4, r0, DBAT3L_VAL@h
		ori    r4, r4, DBAT3L_VAL@l
		addis  r3, r0, DBAT3U_VAL@h
		ori    r3, r3, DBAT3U_VAL@l
		mtspr  dbat3l, r4
		mtspr  dbat3u, r3
		isync

 
   // As a last step, the MMU needs to be enabled by setting the instruction
   // and data translation bits in the MSR. 

//	instruction_address_translation_on
		mfmsr  r5
		ori    r5, r5, 0x0020
		mtmsr  r5
		isync

//	data_address_translation_on
		mfmsr  r5
		ori    r5, r5, 0x0010
		mtmsr  r5
		isync

   mtspr    LR,r9      // restore original Link Register value 

   bclr  20,0           // jump unconditionally to effective address in Link
                        // register
}

//########################################################################
// Function: AddrTranslationOff
//
// Description: This function will clear the instruction address translation
//				bit in MSR and the data address translation bit in MSR
//
//########################################################################        

asm void AddrTranslationOff()
{
   nofralloc

   //	instruction_address_translation_off
   mfmsr  r5
   andi.  r5, r5, 0xFFDF	// clear address data translation bit in MSR
   mtmsr  r5
   isync

   //	data_address_translation_off
   mfmsr  r5
   andi.  r5, r5, 0xFFEF	// clear instruction data translation bit in MSR
   mtmsr  r5
   isync

   bclr     20,0        // jump unconditionally to effective address in Link
                        // register
}



//########################################################################
// Function: InvalidateBATs
//
// Description: This function will clear the Vp and Vs bits. These bits are
//              both valid bits and the one that is checked during the 
//              translation process depends on the state of the MSR[PR]
//              bit. Here's the rule:
//
//                 MSR[PR] = 0 corresponds to supervisor mode; in this mode,
//                 Vs is checked.
//
//                 MSR[PR] = 1 corresponds to user mode; in this mode, Vp
//                 is checked.
//
//              Both bits will be cleared in all 4 IBAT and all 4 DBAT
//              registers because the state of these bits are not
//              guaranteed upon power-up reset.
//
//########################################################################        

asm void InvalidateBATs()
{
   nofralloc


   addis    r0,0,0      // load 0 into R0

   isync
   mtspr    DBAT0U,r0   // Data bat register 0 upper
   isync
   mtspr    DBAT1U,r0   // Data bat register 1 upper
   isync
   mtspr    DBAT2U,r0   // Data bat register 2 upper
   isync
   mtspr    DBAT3U,r0   // Data bat register 3 upper
   isync

   mtspr    IBAT0U,r0   // Instruction bat register 0 upper
   isync
   mtspr    IBAT1U,r0   // Instruction bat register 1 upper
   isync
   mtspr    IBAT2U,r0   // Instruction bat register 2 upper
   isync
   mtspr    IBAT3U,r0   // Instruction bat register 3 upper
   isync

   bclr     20,0        // jump unconditionally to effective address in Link
                        // register
}



//###########################################################################
// Function: InvalidateTLBs
//
// Description:
//
//  All 32 TLBs are invalidated. The tlbie instruction will clear the valid
//  bit for each TLB entry. Each TLB entry is indexed by effective address
//  A15 through A19. This example is not using the PowerPC instruction
//  tlbia because the 603 core does not support it. So traversing through all
//  32 entries is the only method.
//
//########################################################################        

asm void InvalidateTLBs()
{
   nofralloc


   //-----------------------------------------------------------------------
   // Loop 32 times, incrementing effective address A15-A19 using the tlbie
   // mnemonic. 
   //-----------------------------------------------------------------------

   addi     r5,0,32
   mtspr    CTR,r5            // Load CTR with 32. 

   addi     r3,0,0            // Use r3 as the tlb index
      
tlb_write_loop:

   tlbie    r3                // invalidate the tlb entry
   sync
   addi     r3,r3,0x1000      // increment the index
    
   bc       16,0,tlb_write_loop   // Decrement CTR, then branch if the 
                                  // decremented CTR is not equal to 0      


   bclr  20,0    // jump unconditionally to effective address in Link
                 // register
}



//###########################################################################
// Function:  FlushDataCache
//
// Description: This function flushes the data cache. For the 603ev, there is 
//              no direct way to do this. The blocks/cache lines cannot be 
//              flushed incrementally in a direct fashion unless all effective
//              addresses cached are known in the data cache. Since this is  
//              too difficult to know, this function will traverse through all 
//              possible effective addresses in the user data space in 
//              external memory with a dcbf (data cache block flush) mnemonic.
//              In this way, no data location will be missed.
//
// History:
//
// 1/9/99    Initial    jay  
//
//########################################################################        

asm void FlushDataCache()
{
   nofralloc


	addis    r3,0,0         // Load the start address of 0x00000000

   //--------------------------------------------------------------------
   // I chose a RAM address of 0x00013000 because I figure that my data 
   // requirements won't exceed this memory limit.
   //--------------------------------------------------------------------

	addis    r5,0,0x0001      
   addi     r5,r5,0x3000   // Load the end address of 0x00013000

FlushAgain:

	cmp	   cr0,0,r3,r5         // Compare 2 unsigned words
	bge	   FlushDone         // go to done

   //--------------------------------------------------------------------
   // flush the next effective address if it exists in the cache. If it 
   // doesn't, the flush command will be ignored. If it does, the block 
   // value will be copied back to RAM and the block will be invalidated.
   //---------------------------------------------------------------------

   dcbf     0,r3              

	addi	   r3,r3,0x4         // increment by a word
	b	      FlushAgain        // repeat

FlushDone:

   bclr  20,0           // jump unconditionally to effective address in Link
                        // register
}

//###########################################################################
// Function: DisableDataCache
//
// Description: This function disables the data cache only by clearing the 
//              DCE bit in the HID0 register and setting DCFI bit. Note that
//				by executing this function, all modified blocks will be destroyed.
//
//########################################################################        

asm void DisableDataCache()
{
   nofralloc

   mfspr  r5,hid0
   ori    r5,r5,0x0400		// set hid0 DCFI bits
   sync
   mtspr  hid0,r5
   andi.  r0, r0, 0xBBFF	// clear hid0 DCE and DCFI bits
   sync
   mtspr  hid0,r5

   bclr  20,0           // jump unconditionally to effective address in Link
                        // register
}


//###########################################################################
// Function:  DisableInstCache
//
// Description: This function disables the instruction cache by clearing the
//              ICE bit in the HID0 register and sets ICFI bit in HID0
//
//########################################################################        

asm void DisableInstCache()
{
   nofralloc

   mfspr  r5, hid0
   ori    r5, r5, 0x0800   // set hid0 ICFI bit
   isync
   mtspr  hid0, r5
   andi.  r5, r5, 0x77FF	// clear hid0 ICE and ICFI bits
   isync
   mtspr  hid0, r5

   bclr  20,0           // jump unconditionally to effective address in Link
                        // register
}