init_mmu_cache.c

mpc2872系列的usb controller产生sof源码

#include "init_mmu_cache.h"

//----------------------------------------------------------------------------
//                                                                       
//  DESCRIPTION: 
//                                                                       
//  This file contains the initialization software for:
//
//   - Dcache (Data Cache) and Icache (Instruction Cache).
//
//   - MMU (Memory Management Unit)
//
//
//----------------------------------------------------------------------------

asm void mmu_cache_init();
asm void init_caches();
asm void EnableAndInvalidateDataCache();
asm void EnableAndInvalidateInstCache();
asm void init_bat_mmu();
asm void InvalidateBATs();
asm void InvalidateTLBs();
asm void AddrTranslationOff();
asm void FlushDataCache();
asm void DisableDataCache();
asm void DisableInstCache(); 
 
#pragma section code_type ".init"


asm void mmu_cache_init()
{
	nofralloc
	
   mfspr    r7,LR        // Save the Link Register value. The link register's
                          // value will be restored so that this function 
                          // can return to the calling address.
   // Disable Caches
   bl		DisableInstCache
   bl		DisableDataCache
   
   // Initialize MMU
   bl       init_bat_mmu

   // Initialize Instruction and Caches
   bl       init_caches

   mtspr    LR,r7      // restore original Link Register value 

   bclr     20,0        // jump unconditionally to effective address in Link
                        // register
}


//###########################################################################
// Function: init_caches
//
// Description: Initializes the Data/Instruction Caches. 
//
//###########################################################################        


asm void init_caches()
{
   nofralloc

   mfspr    r8,LR        // Save the Link Register value

   // Enable the Instruction Cache 
   bl    EnableAndInvalidateInstCache

   // Enable the Data Cache 
   bl    EnableAndInvalidateDataCache

   mtspr    LR,r8      // restore original Link Register value 

   bclr  20,0           // jump unconditionally to effective address in Link
                        // register
}



//###########################################################################
// Function: EnableAndInvalidateDataCache
//
// Description: This function is used to initialize the Data cache to a start
//              state. This is done by ensuring that data cache is enabled by
//              explicitly enabling it and invalidating all cache lines or 
//              blocks. Note that by executing this function, all modified
//              blocks will be destoyed.
//########################################################################        

asm void EnableAndInvalidateDataCache()
{
   nofralloc

#if DATA_CACHE_ON
//	invalidate_enable_L1_dcache
            
   mfspr r5,HID0         
   ori   r5,r5,0x4400   // Set DCE and DCFI bit
   andi. r4,r5,0xFBFF   // Clear the DCFI bit for the final store
   mtspr HID0,r5
   isync
   sync

   mtspr HID0,r4        // Store the final value
   isync
   sync

#endif

   bclr  20,0           // jump unconditionally to effective address in Link
                        // register
}


//###########################################################################
// Function: EnableAndInvalidateInstCache
//
// Description: This function first enables the instruction cache and then
//              sets the instruction cache flash invalidate (ICFI) bit in 
//              the HID0 register. This establishes a start state for the 
//              cache.
//
//########################################################################        

asm void EnableAndInvalidateInstCache()
{
   nofralloc

#if INSTRUCTION_CACHE_ON

   //	invalidate_enable_L1_icache
   mfspr r5,HID0        
   ori   r5,r5,0x8800   // Set the ICE and ICFI bit
   andi. r4,r5,0xF7FF   // clear the ICFI bit for the final store
   mtspr HID0,r5
   isync
   sync

   mtspr HID0,r4        // Do the final store
   isync
   sync
#endif

   bclr  20,0           // jump unconditionally to effective address in Link
                        // register
}




//########################################################################
// Function: init_bat_mmu
//
// Description: In the process of determining the physical address from the
//              effective address, there are 3 paths/modes that can be 
//              taken. 
//
//              The first is the Real Address mode where the effective
//              address is equal to the physical address. In this mode, the
//              MMU is turned off and as a default, instruction and data
//              cacheing are enabled for all physical addresses as part of
//              the default WIMG value. The IMMR address space as well as 
//              some I/O space must be data cache inhibited. Data cache must
//              be turned completely off by ensuring that HID0[DCE] is 
//              cleared. HID0[ICE] still needs to be set during instruction
//              cache initializtion.
//
//              The second is Block Address Translation. This MMU mode offers
//              memory characterization and control on blocks of memory from
//              128 Kbyte to 256 Mbytes in size. The drawback to this mode
//              is the limited number of blocks that can be considered in 
//              the translation process. The MPC8260 only offers 4 different
//              blocks of memory that can be managed. That is, 4 blocks for
//              data and 4 for instructions.
//
//              The last mode is Page Address Translation. This mode is the
//              most complicated and offers the finest granularity in terms
//              memory management. Pages are 4 Kbytes in size and can be 
//              managed with the ability to operate in a virtual memory space
//              as far as the application/operating system software is 
//              conserned. This virtual space is expanded from 2^32 bytes to 
//              2^52 bytes. Page Address Translation is useful for operating 
//              systems that need to swap out tasks or programs from disk 
//              storage which need to run in the same physical memory space. 
//              This swapping requires searching tables and developing soft-
//              ware for interrupt routines to insert new Page Table entries 
//              when the effective address is not found in the on-chip Page 
//              Translation table. Software is also required to do the 
//              task/program swapping as well.
//
//              This example does not require the complexity of page 
//              translation yet we still want to take advantage of memory
//              management. Block Address Translation is our choice. 
//
//              The Block Address Translation (BAT) registers will be 
//              allocated in the following manner:
//
//                 -> IBAT0 and DBAT0 - 60x SDRAM 
//
//                       - Read/Write capability
//                       - Write-Through is disabled.
//                       - Cacheing enabled
//                       - No requirements to enforce memory coherency.
//                       - Address space is unguarded
//
//                 -> DBAT1 - PCI
//
//                       - Read/Write capability
//                       - Write-Through is disabled. 
//                       - Cacheing disabled
//                       - No requirements to enforce memory coherency.
//                       - Address space is unguarded
//
//                 -> DBAT2 - Board Status and Control Registers 0-2
//                          - Internal Memory Map Registers (IMMR) space
//
//                       - Read/Write capability
//                       - Write-Through is enabled. 
//                       - Cacheing disabled
//                       - No requirements to enforce memory coherency.
//                       - Address space is unguarded
//
//                 -> IBAT3 and DBAT3- Flash ROM memory (8 Mbyte)
//
//                       - Read/Write capability. The ability to write has
//                         been added for flash reprogramming.
//                       - Write-Through is enabled
//                       - Instruction Cacheing enabled. Data Cacheing 
//                         disabled.
//                       - No requirements to enforce memory coherency.
//                       - Address space is unguarded
//
//########################################################################        

asm void init_bat_mmu()
{
   nofralloc

   mfspr    r9,LR        // Save the Link Register value. The link register's
                          // value will be restored so that this function 
                          // can return to the calling address.

   // Turn off the address translation
   bl	AddrTranslationOff
   
   // The 603e BAT registers are not initialized by the hardware after the 
   // power-up or reset sequence. Consequently, all valid bits in both 
   // instruction and data BAT areas must be cleared before setting any BAT 
   // area for the first time. This is true regardless of whether address 
   // translation is enabled. 
   bl    InvalidateBATs    // clear the valid bits on all 8   

   // Invalidate all TLB entries: This needs to be done because Translation
   // Lookaside Buffers valid bits are undefined at reset. The MMU comes out 
   // of reset disabled but if the MMU were enabled and TLB's were not 
   // invalidated first, erratic behavior would result.
   bl InvalidateTLBs      // Invalidate all TLBs

   //	setup_ibats
		addis  r0, r0, 0x0000
		addis  r4, r0, IBAT0L_VAL@h
		ori    r4, r4, IBAT0L_VAL@l
		addis  r3, r0, IBAT0U_VAL@h
		ori    r3, r3, IBAT0U_VAL@l
		mtspr  ibat0l, r4
		mtspr  ibat0u, r3
		isync

		addis  r4, r0, IBAT1L_VAL@h
		ori    r4, r4, IBAT1L_VAL@l
		addis  r3, r0, IBAT1U_VAL@h
		ori    r3, r3, IBAT1U_VAL@l
		mtspr  ibat1l, r4
		mtspr  ibat1u, r3
		isync

		addis  r4, r0, IBAT2L_VAL@h
		ori    r4, r4, IBAT2L_VAL@l
		addis  r3, r0, IBAT2U_VAL@h
		ori    r3, r3, IBAT2U_VAL@l
		mtspr  ibat2l, r4
		mtspr  ibat2u, r3
		isync

		addis  r4, r0, IBAT3L_VAL@h
		ori    r4, r4, IBAT3L_VAL@l
		addis  r3, r0, IBAT3U_VAL@h
		ori    r3, r3, IBAT3U_VAL@l
		mtspr  ibat3l, r4