📄 mpc8272.h
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/*---------------------------------------------------------------------*/
/* A note about the pram union: */
/* The pram area has been broken out three ways for clean access into */
/* certain peripherals' spaces. This arrangement allows programmers */
/* flexibility of usage in terms of being able to change which */
/* peripheral is being accessed by simply changing an array value. */
/* Given the interweaving of certain peripherals' pram areas, this */
/* would not be possible with only one large pram structure. */
/* */
/* SERIALS - For accessing SCC, non-ATM FCC, and MCC pram */
/* ATM - For accessing ATM FCC pram */
/* STANDARD - For accessing timers, revnum, d_ptr, RAND, and the pram */
/* base pointers of the SMCs, IDMAs, SPI, and I2C */
/*---------------------------------------------------------------------*/
union
{
/*for access to the PRAM structs for SCCs, FCCs, and QMC */
struct serials
{
t_Scc_Pram scc_pram[4]; /* Note there is no SCC2 */
t_Fcc_Pram fcc_pram[2];
uchar reserved1[0x900];
} serials;
/* for access to ATM PRAM structs */
struct atm
{
uchar reserved2[0x400];
t_Atm_Pram atm_pram[2];
uchar reserved3[0xa00];
} atm;
/* for access to the memory locations holding user-defined
base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */
struct standard
{
uchar scc1[0x100];
uchar reserved0[0x100];
uchar scc3[0x100];
uchar scc4[0x100];
uchar fcc1[0x100];
uchar fcc2[0x100];
uchar reserved1[0x100];
uchar reserved2[0x80];
uchar reserved3[0x7c];
uchar smc1[0x2];
uchar reserved4[0x2];
uchar reserved5[0x80];
uchar reserved6[0x7c];
uchar smc2[0x2];
uchar idma2[0x2];
uchar reserved7[0xfc];
uchar spi[0x2];
uchar idma3[0x2];
uchar reserved8[0xe0];
uchar timers[0x10];
uchar Rev_num[0x2];
uchar D_ptr[0x2];
uchar reserved9[0x4];
uchar rand[0x4];
uchar i2c[0x2];
uchar reserved10[0x2];
uchar usb[0x100];
uchar reserved11[0x400];
} standard;
} pram;
uchar cpm_ram_dpram_2[0x1000];
uchar reserved12[0x6000]; /* Reserved area */
/* siu */
uword siu_siumcr; /* SIU Module Configuration Register */
uword siu_sypcr; /* System Protection Control Register */
uchar reserved13[0x6]; /* Reserved area */
ushort siu_swsr; /* Software Service Register */
/* buses */
uchar reserved14[0x14]; /* Reserved area */
uword bcr; /* Bus Configuration Register */
uchar ppc_acr; /* Arbiter Configuration Register */
uchar reserved15[0x3]; /* Reserved area */
uword ppc_alrh; /* Arbitration Level Reg. (First clients) */
uword ppc_alrl; /* Arbitration Level Reg. (Next clients) */
uchar lcl_acr; /* LCL Arbiter Configuration Register */
uchar reserved16[0x3]; /* Reserved area */
uword lcl_alrh; /* LCL Arbitration Level Reg. (First clients) */
uword lcl_alrl; /* LCL Arbitration Level Register (Next clients) */
uword tescr1; /* PPC bus transfer error status control reg. 1 */
uword tescr2; /* PPC bus transfer error status control reg. 2 */
uword reserved17[0x2]; /* Reserved */
uword pdtea; /* PPC bus DMA Transfer Error Address */
uchar pdtem; /* PPC bus DMA Transfer Error MSNUM */
uchar reserved18[0xAB]; /* Reserved area */
/* memc */
struct memc_regs
{
uword br; /* Base Register */
uword or; /* Option Register */
} memc_regs[8];
uchar reserved19[0x28]; /* Reserved area */
uword memc_mar; /* Memory Address Register */
uchar reserved20[0x4]; /* Reserved area */
uword memc_mamr; /* Machine A Mode Register */
uword memc_mbmr; /* Machine B Mode Register */
uword memc_mcmr; /* Machine C Mode Register */
uword memc_mdmr; /* Machine D Mode Register */
uchar reserved21[0x4]; /* Reserved area */
ushort memc_mptpr; /* Memory Periodic Timer Prescaler */
uchar reserved22[0x2]; /* Reserved area */
uword memc_mdr; /* Memory Data Register */
uchar reserved23[0x4]; /* Reserved area */
uword memc_psdmr; /* PowerPC Bus SDRAM machine Mode Register */
uword reserved24; /* Reserved */
uchar memc_purt; /* PowerPC Bus assigned VUPM Refresh Timer */
uchar reserved25[0x3]; /* Reserved area */
uchar memc_psrt; /* PowerPC Bus assigned SDRAM Refresh Timer */
uchar reserved26[0xB]; /* Reserved area */
uword memc_immr; /* Internal Memory Map Register */
/* pci */
uword pcibr0; /* Base address+valid for window 1 */
uword pcibr1; /* Base address+valid for window 2 */
uword secbr; /* SEC address base register */
uword reserved27; /* Reserved area */
uword secmr; /* SEC mask register */
uword reserved28; /* Reserved */
uword pcimsk0; /* Mask for window 1 */
uword pcimsk1; /* Mask for window 2 */
uchar reserved29[0x54]; /* Reserved area */
/* si_timers */
ushort si_timers_tmcntsc; /* Time Counter Status and Control Register */
uchar reserved30[0x2]; /* Reserved area */
uword si_timers_tmcnt; /* Time Counter Register */
uword si_timers_tmcntsec; /* Time Counter Seconds */
uword si_timers_tmcntal; /* Time Counter Alarm Register */
uchar reserved31[0x10]; /* Reserved area */
ushort si_timers_piscr; /* Periodic Interrupt Status and Control Reg*/
uchar reserved32[0x2]; /* Reserved area */
uword si_timers_pitc; /* Periodic Interrupt Count Register */
uword si_timers_pitr; /* Periodic Interrupt Timer Register */
uchar reserved33[0x1E4]; /* Reserved area */
/* pci registers */
uword omisr; /* Outbound interrupt status register */
uword omimr; /* Outbound interrupt mask register */
uword reserved34[0x2]; /* Reserved area */
uword ifqpr; /* Inbound FIFO queue port register */
uword ofqpr; /* Outbound FIFO queue port register */
uword reserved35[0x2]; /* Reserved area */
uword imr0; /* Inbound message register 0 */
uword imr1; /* Inbound message register 1 */
uword omr0; /* Outbound message register 0 */
uword omr1; /* Outbound message register 1 */
uword odr; /* Outbound doorbell register */
uword reserved36; /* Reserved area */
uword idr; /* Inbound doorbell register */
uchar reserved37[0x14]; /* Reserved area */
uword imisr; /* Inbound message interrupt status */
uword imimr; /* Inbound message interrupt mask */
uword reserved38[0x6]; /* Reserved area */
uword ifhpr; /* Inbound free_FIFO head pointer */
uword reserved39; /* Reserved area */
uword iftpr; /* Inbound free_FIFO tail pointer */
uword reserved40; /* Reserved area */
uword iphpr; /* Inbound post_FIFO head pointer */
uword reserved41; /* Reserved area */
uword iptpr; /* Inbound post_FIFO tail pointer */
uword reserved42; /* Reserved area */
uword ofhpr; /* Outbound free_FIFO head pointer */
uword reserved43; /* Reserved area */
uword oftpr; /* Outbound free_FIFO tail pointer */
uword reserved44; /* Reserved area */
uword ophpr; /* Outbound post_FIFO head pointer */
uword reserved45; /* Reserved area */
uword optpr; /* Outbound post_FIFO tail pointer */
uword reserved46[2]; /* Reserved area */
uword mucr; /* Message unit control register */
uword reserved47[2]; /* Reserved area */
uword qbar; /* Queue base address register */
uword reserved48[3]; /* Reserved area */
uword dmamr0; /* DMA 0 mode register */
uword dmasr0; /* DMA 0 status register */
uword dmacdar0; /* DMA 0 current descriptor address */
uword reserved990; /* Reserved area */
uword dmasar0; /* DMA 0 source address register */
uword reserved991; /* Reserved area */
uword dmadar0; /* DMA 0 destination address register */
uword reserved992; /* Reserved area */
uword dmabcr0; /* DMA 0 byte count register */
uword dmandar0; /* DMA 0 next descriptor address */
uword reserved49[22]; /* Reserved area */
uword dmamr1; /* DMA 1 mode register */
uword dmasr1; /* DMA 1 status register */
uword dmacdar1; /* DMA 1 current descriptor address */
uword reserved50; /* Reserved area */
uword dmasar1; /* DMA 1 source address register */
uword reserved51; /* Reserved area */
uword dmadar1; /* DMA 1 destination address register */
uword reserved52; /* Reserved area */
uword dmabcr1; /* DMA 1 byte count register */
uword dmandar1; /* DMA 1 next descriptor address */
uword reserved53[22]; /* Reserved area */
uword dmamr2; /* DMA 2 mode register */
uword dmasr2; /* DMA 2 status register */
uword dmacdar2; /* DMA 2 current descriptor address */
uword reserved54; /* Reserved area */
uword dmasar2; /* DMA 2 source address register */
uword reserved55; /* Reserved area */
uword dmadar2; /* DMA 2 destination address register */
uword reserved56; /* Reserved area */
uword dmabcr2; /* DMA 2 byte count register */
uword dmandar2; /* DMA 2 next descriptor address */
uword reserved57[22]; /* Reserved area */
uword dmamr3; /* DMA 3 mode register */
uword dmasr3; /* DMA 3 status register */
uword dmacdar3; /* DMA 3 current descriptor register */
uword reserved58; /* Reserved area */
uword dmasar3; /* DMA 3 source address register */
uword reserved59; /* Reserved area */
uword dmadar3; /* DMA 3 destination address register */
uword reserved60; /* Reserved area */
uword dmabcr3; /* DMA 3 byte count register */
uword dmandar3; /* DMA 3 next descriptor address */
uword reserved61[86]; /* Reserved area */
uword potar0; /* PCI outbound translation address */
uword reserved62; /* Reserved area */
uword pobar0; /* PCI outbound base address register */
uword reserved63; /* Reserved area */
uword pocmr0; /* PCI outbound comparison mask */
uword reserved64; /* Reserved area */
uword potar1; /* PCI outbound translation address */
uword reserved65; /* Reserved area */
uword pobar1; /* PCI outbound base address register */
uword reserved66; /* Reserved area */
uword pocmr1; /* PCI outbound comparison mask */
uword reserved67; /* Reserved area */
uword potar2; /* PCI outbound translation address */
uword reserved68; /* Reserved area */
uword pobar2; /* PCI outbound base address register */
uword reserved69; /* Reserved area */
uword pocmr2; /* PCI outbound comparison mask */
uword reserved70[13]; /* Reserved area */
uword ptcr; /* Discard timer control register */
uword gpcr; /* General purpose control register */
uword pci_gcr; /* PCI general control register */
uword esr; /* Error status register */
uword emr; /* Error mask register */
uword ecr; /* Error control register */
uword pci_eacr; /* PCI error address capture register */
uword reserved71; /* Reserved area */
uword pci_edcr; /* PCI error data capture register */
uword pci_eccr; /* PCI error control capture register */
uword reserved72[12]; /* Reserved area */
uword pitar1; /* PCI inbound translation address */
uword reserved73; /* Reserved area */
uword pibar1; /* PCI inbound base address register1 */
uword reserved74; /* Reserved area */
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