ad9851.syr

经典的dds发生器ad9851vhdl的并行通信代码

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 1.14 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
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--> Reading design: ad9851.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
     5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "ad9851.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "ad9851"
Output Format                      : NGC
Target Device                      : xc2s100-6-pq208

---- Source Options
Top Module Name                    : ad9851
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : ad9851.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/C-VHDL/vhdl/ad9851-1/key.vhd" in Library work.
Architecture behavioral of Entity key is up to date.
Compiling vhdl file "E:/C-VHDL/vhdl/ad9851-1/ad9851.vhd" in Library work.
Architecture behavioral of Entity ad9851 is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ad9851> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/C-VHDL/vhdl/ad9851-1/ad9851.vhd" line 58: The following signals are missing in the process sensitivity list:
   keyf.
Entity <ad9851> analyzed. Unit <ad9851> generated.

Analyzing Entity <key> (Architecture <behavioral>).
Entity <key> analyzed. Unit <key> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <key>.
    Related source file is "E:/C-VHDL/vhdl/ad9851-1/key.vhd".
    Found 1-bit register for signal <keyout>.
    Found 24-bit 4-to-1 multiplexer for signal <$n0003>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0004>.
    Found 24-bit adder for signal <$n0005> created at line 47.
    Found 24-bit register for signal <qq>.
    Summary:
	inferred  25 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred  25 Multiplexer(s).
Unit <key> synthesized.


Synthesizing Unit <ad9851>.
    Related source file is "E:/C-VHDL/vhdl/ad9851-1/ad9851.vhd".
WARNING:Xst:653 - Signal <control<0>> is used but never assigned. Tied to value 00001001.
INFO:Xst:1435 - HDL ADVISOR - Unable to extract a block RAM for signal <control>. The read/write synchronization appears to be READ_FIRST and is not available for the selected family. A distributed RAM will usually be created instead. To take advantage of block RAM resources, you may want to revisit your RAM synchronization or check available device families.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | $n0007 (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | st0                                            |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8x8-bit ROM for signal <$n0015> created at line 117.
    Found 1-bit register for signal <dds_wclk>.
    Found 1-bit register for signal <dds_fqud>.
    Found 1-bit register for signal <dds_reset>.
    Found 8-bit register for signal <dds_data>.
    Found 8-bit 5-to-1 multiplexer for signal <$n0005> created at line 81.
    Found 16-bit comparator less for signal <$n0008> created at line 71.
    Found 16-bit comparator less for signal <$n0009> created at line 82.
    Found 3-bit comparator less for signal <$n0010> created at line 91.
    Found 8-bit 8-to-1 multiplexer for signal <$n0016> created at line 117.
    Found 8-bit 8-to-1 multiplexer for signal <$n0020> created at line 117.
    Found 8-bit 8-to-1 multiplexer for signal <$n0021> created at line 117.
    Found 3-bit adder for signal <$n0026> created at line 116.
    Found 16-bit adder for signal <$n0027> created at line 83.
    Found 3-bit adder for signal <$n0028> created at line 93.
    Found 16-bit comparator less for signal <$n0029> created at line 100.
    Found 16-bit comparator greatequal for signal <$n0031> created at line 82.
    Found 16-bit register for signal <cnt>.
    Found 3-bit register for signal <cnt2>.
    Found 32-bit register for signal <control<1:4>>.
    Found 3-bit up counter for signal <kk>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred  62 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   5 Comparator(s).
	inferred  32 Multiplexer(s).
Unit <ad9851> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 8x8-bit ROM                                           : 1
# Adders/Subtractors                                   : 4
 16-bit adder                                          : 1
 24-bit adder                                          : 1
 3-bit adder                                           : 2
# Counters                                             : 1
 3-bit up counter                                      : 1
# Registers                                            : 12
 1-bit register                                        : 4
 16-bit register                                       : 1
 24-bit register                                       : 1
 3-bit register                                        : 1
 8-bit register                                        : 5
# Comparators                                          : 5
 16-bit comparator greatequal                          : 1
 16-bit comparator less                                : 3
 3-bit comparator less                                 : 1
# Multiplexers                                         : 6
 1-bit 4-to-1 multiplexer                              : 1
 24-bit 4-to-1 multiplexer                             : 1
 8-bit 5-to-1 multiplexer                              : 1
 8-bit 8-to-1 multiplexer                              : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <state> on signal <state[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 st0   | 00
 st1   | 01
 st2   | 10
-------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 1
# ROMs                                                 : 1
 8x8-bit ROM                                           : 1
# Adders/Subtractors                                   : 4
 16-bit adder                                          : 1
 24-bit adder                                          : 1
 3-bit adder                                           : 2
# Counters                                             : 1
 3-bit up counter                                      : 1
# Registers                                            : 89
 Flip-Flops                                            : 89
# Comparators                                          : 5
 16-bit comparator greatequal                          : 1
 16-bit comparator less                                : 3
 3-bit comparator less                                 : 1
# Multiplexers                                         : 6
 1-bit 4-to-1 multiplexer                              : 1
 24-bit 4-to-1 multiplexer                             : 1
 8-bit 5-to-1 multiplexer                              : 1
 8-bit 8-to-1 multiplexer                              : 3

=========================================================================