key.vhd

经典的dds发生器ad9851vhdl的并行通信代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:15:58 05/02/2007 
-- Design Name: 
-- Module Name:    key - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity key is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           keyout : out  STD_LOGIC;
           keyin : in  STD_LOGIC);
end key;

architecture Behavioral of key is

begin
process(clk,reset,keyin)
   variable qq:integer range 0 to 9600000;              --start transfer key
		begin
		if reset='0' then qq:=0;
		                  keyout<='0';
       elsif clk'event and clk='1' then
		    if keyin='0' then
			  qq:=qq+1;
			    if qq=2400000 then 
				  keyout<='1';
				  elsif qq=9600000 then
				  qq:=0;keyout<='0';
				  end if;
			   else
					keyout<='0';
					qq:=0;
				end if;
			end if;
	end process;


end Behavioral;