ad9851.vhd

经典的dds发生器ad9851vhdl的并行通信代码

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    23:05:42 06/15/2007 
-- Design Name: 
-- Module Name:    ad9851 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ad9851 is
    Port ( clk : in  STD_LOGIC;
	        rst:  in std_logic;
			  keyin: in std_logic;
			  dds_wclk: out std_logic;
			  dds_fqud: out std_logic;
			  dds_reset: out std_logic;
			  bitt: out std_logic_vector(3 downto 0);
			  seg: out std_logic_vector(7 downto 0);
			  dds_data: out std_logic_vector( 7 downto 0));
end ad9851;

architecture Behavioral of ad9851 is
component key is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           keyout : out  STD_LOGIC;
           keyin : in  STD_LOGIC);
end component;
type states is (st0,st1,st2);
signal state:states:=st0;
type rom is array( 0 to 4) of std_logic_vector( 7 downto 0);
signal control: rom:=("00001001","00001110","00111000","11100011","10001110");
signal keyf: std_logic;
type state is(idle,s_ad9851,s_ads7816,s_ad9731,s_tlc55101,s_ask,s_fsk,
               -----------------floor2---------------
              ad9851_set_f,ad9851_fm,ad9851_scan_f,
				  ads7816_dc,ads7816_sample,
				  ad9731_pulse,ad9731_juchi,ad9731_sine,ad9731_7816,ad9731_55101,
				  tlc55101_dc,tlc55101_sample,
				  -------------------floor3--------------
				  ad9851_set_f1,ad9731_set_f);
signal current_state:state:=idle;
begin
bitt<="0011";

process(clk,rst)									--??????
variable cnt:integer range 0 to 50000:=0;
variable cnt2:integer range 0 to 5:=0;
begin
	if rst='0' or keyf='0' then
		state<=st0;
		dds_wclk<='0';
		dds_fqud<='0';
		dds_reset<='0';
	elsif clk'event and clk='1' then
		case state is
			when st0=>							 --DDS??
						dds_reset<='1';
						if cnt<50000 then				 
							cnt:=cnt+1;
							state<=st0;
						else
							cnt:=0;
							state<=st1;
							dds_reset<='0';
							cnt2:=0;
						end if;
			when st1=>							 --DDS???,???
						dds_data<=control(cnt2);
						if cnt<5 then
							cnt:=cnt+1;
							if cnt=2 then
								dds_wclk<='1';
							elsif cnt=4 then
								dds_wclk<='0';
							end if;
						else
							cnt:=0;										
							if cnt2<4 then
								state<=st1;
								cnt2:=cnt2+1;
							else
								state<=st2;
								cnt2:=0;
							end if;
						end if;						
			when st2=>							  --??,????
						if cnt<1 then
							dds_fqud<='1';
							cnt:=cnt+1;
						else
							dds_fqud<='0';
						end if;
	
			when others=>null;
		end case;
	end if;
end process;
------change f-------
process(keyf)
variable kk: integer range 0 to 7:=4;
begin 
  if keyf'event and keyf='1' then 
    kk:=kk+1;
	 case kk is
	 when 0 => control(1)<="00001110";---------10M
	    
	 when 1 => control(1)<="00000000";---------10HZ
	           control(2)<="00000000";
				  control(3)<="00000000";
				  control(4)<="11101110";
	 when 2 => control(1)<="00000000";---------100HZ
	           control(2)<="00000000";
				  control(3)<="00001001";
				  control(4)<="01010010";
	 when 3 => control(1)<="00000000";---------1K
	           control(2)<="00000000";
				  control(3)<="01011101";
				  control(4)<="00110100";
	 when 4 => control(1)<="00000000";---------10K
	           control(2)<="00000011";
				  control(3)<="10100100";
				  control(4)<="00001000";
	 when 5 => control(1)<="00000000";---------20K
	           control(2)<="00000111";
				  control(3)<="01001000";
				  control(4)<="00010000";
	 when 6 => control(1)<="00001110";---------10M
	           control(2)<="00001110";
				  control(3)<="00001110";
				  control(4)<="00001110";
	 when 7 => control(1)<="00001110";---------10HZ
	           control(2)<="00001110";
				  control(3)<="00001110";
				  control(4)<="00001110";
	 when others =>null;
	 end case;
	end if;
	seg<=conv_std_logic_vector(kk,8);
end process;
process(clk1ms,data0,data1,data2,data3)
 variable kk: integer range 0 to 3 ;
 variable data: std_logic_vector(3 downto 0);
 begin 
   if rising_edge(clk1ms) then 
	   kk:=kk+1;
		case kk is 
		when 0 => bitt<="1110";
		          data:=data3;
		when 1 => bitt<="1101";
		          data:=data2;
		when 2 => bitt<="1011";
		          data:=data1;
		when 3 => bitt<="0111";
		          data:=data0;
		when others => null;
		end case;
	 end if;
	 
     case data is
         when"0000"=>seg<="11000000";--0
	      when"0001"=>seg<="11111001";--1
	      when"0010"=>seg<="10100100";--2
			when"0011"=>seg<="10110000";--3
			when"0100"=>seg<="10011001";--4
			when"0101"=>seg<="10010010";--5
			when"0110"=>seg<="10000010";--6
			when"0111"=>seg<="11111000";--7
			when"1000"=>seg<="10000000";--8
			when"1001"=>seg<="10010000";--9 
			----------no d
			when"1010"=>seg<="10011000";--a
         when"1011"=>seg<="10000011";--b
         when"1100"=>seg<="11000110";--c
         when"1101"=>seg<="10100001";--d 			
			when"1110"=>seg<="10000100";--e
			when others=>seg<="11111111";--No signal; 
       end case; 
end process;
u1: key port map(clk=>clk,reset=>rst,keyin=>keyin,keyout=>keyf);
end Behavioral;