📄 au1200.h
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#define AU1200_TOY_MATCH1_INT 16
#define AU1200_TOY_MATCH2_INT 17
#define AU1200_RTC_INT 18
#define AU1200_RTC_MATCH0_INT 19
#define AU1200_RTC_MATCH1_INT 20
#define AU1200_RTC_MATCH2_INT 21
#define AU1200_NAND_INT 23
#define AU1200_GPIO_204 24
#define AU1200_GPIO_205 25
#define AU1200_GPIO_206 26
#define AU1200_GPIO_207 27
#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
#define AU1200_USB_INT 29
#define AU1200_LCD_INT 30
#define AU1200_MAE_BOTH_INT 31
#define AU1000_GPIO_0 32
#define AU1000_GPIO_1 33
#define AU1000_GPIO_2 34
#define AU1000_GPIO_3 35
#define AU1000_GPIO_4 36
#define AU1000_GPIO_5 37
#define AU1000_GPIO_6 38
#define AU1000_GPIO_7 39
#define AU1000_GPIO_8 40
#define AU1000_GPIO_9 41
#define AU1000_GPIO_10 42
#define AU1000_GPIO_11 43
#define AU1000_GPIO_12 44
#define AU1000_GPIO_13 45
#define AU1000_GPIO_14 46
#define AU1000_GPIO_15 47
#define AU1000_GPIO_16 48
#define AU1000_GPIO_17 49
#define AU1000_GPIO_18 50
#define AU1000_GPIO_19 51
#define AU1000_GPIO_20 52
#define AU1000_GPIO_21 53
#define AU1000_GPIO_22 54
#define AU1000_GPIO_23 55
#define AU1000_GPIO_24 56
#define AU1000_GPIO_25 57
#define AU1000_GPIO_26 58
#define AU1000_GPIO_27 59
#define AU1000_GPIO_28 60
#define AU1000_GPIO_29 61
#define AU1000_GPIO_30 62
#define AU1000_GPIO_31 63
#define UART0_ADDR 0xB1100000
#define UART1_ADDR 0xB1200000
#ifdef CONFIG_MIPS_PB1200_MOCKUP
#define USB_OHCI_BASE 0x14020000
#define USB_HOST_CONFIG 0xB4027ffc
#define AU1550_DDMA_INT 3
#define AU1550_ETH0_BASE 0xB0500000
#define AU1550_ETH1_BASE 0xB0510000
#define AU1550_MAC0_ENABLE 0xB0520000
#define AU1550_MAC1_ENABLE 0xB0520004
#define AU1550_MAC0_DMA_INT 27
#define AU1550_MAC1_DMA_INT 28
#define NUM_ETH_INTERFACES 2
#endif
#endif /* CONFIG_SOC_AU1200 */
#define AU1000_LAST_INTC0_INT 31
#define AU1000_LAST_INTC1_INT 63
#define AU1000_MAX_INTR 63
/* Programmable Counters 0 and 1 */
#define SYS_BASE 0xB1900000
#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
#define SYS_CNTRL_E1S (1<<23)
#define SYS_CNTRL_T1S (1<<20)
#define SYS_CNTRL_M21 (1<<19)
#define SYS_CNTRL_M11 (1<<18)
#define SYS_CNTRL_M01 (1<<17)
#define SYS_CNTRL_C1S (1<<16)
#define SYS_CNTRL_BP (1<<14)
#define SYS_CNTRL_EN1 (1<<13)
#define SYS_CNTRL_BT1 (1<<12)
#define SYS_CNTRL_EN0 (1<<11)
#define SYS_CNTRL_BT0 (1<<10)
#define SYS_CNTRL_E0 (1<<8)
#define SYS_CNTRL_E0S (1<<7)
#define SYS_CNTRL_32S (1<<5)
#define SYS_CNTRL_T0S (1<<4)
#define SYS_CNTRL_M20 (1<<3)
#define SYS_CNTRL_M10 (1<<2)
#define SYS_CNTRL_M00 (1<<1)
#define SYS_CNTRL_C0S (1<<0)
/* Programmable Counter 0 Registers */
#define SYS_TOYTRIM (SYS_BASE + 0)
#define SYS_TOYWRITE (SYS_BASE + 4)
#define SYS_TOYMATCH0 (SYS_BASE + 8)
#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
#define SYS_TOYREAD (SYS_BASE + 0x40)
/* Programmable Counter 1 Registers */
#define SYS_RTCTRIM (SYS_BASE + 0x44)
#define SYS_RTCWRITE (SYS_BASE + 0x48)
#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
#define SYS_RTCREAD (SYS_BASE + 0x58)
/* I2S Controller */
#define I2S_DATA 0xB1000000
#define I2S_DATA_MASK (0xffffff)
#define I2S_CONFIG 0xB1000004
#define I2S_CONFIG_XU (1<<25)
#define I2S_CONFIG_XO (1<<24)
#define I2S_CONFIG_RU (1<<23)
#define I2S_CONFIG_RO (1<<22)
#define I2S_CONFIG_TR (1<<21)
#define I2S_CONFIG_TE (1<<20)
#define I2S_CONFIG_TF (1<<19)
#define I2S_CONFIG_RR (1<<18)
#define I2S_CONFIG_RE (1<<17)
#define I2S_CONFIG_RF (1<<16)
#define I2S_CONFIG_PD (1<<11)
#define I2S_CONFIG_LB (1<<10)
#define I2S_CONFIG_IC (1<<9)
#define I2S_CONFIG_FM_BIT 7
#define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
#define I2S_CONFIG_TN (1<<6)
#define I2S_CONFIG_RN (1<<5)
#define I2S_CONFIG_SZ_BIT 0
#define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
#define I2S_CONTROL 0xB1000008
#define I2S_CONTROL_D (1<<1)
#define I2S_CONTROL_CE (1<<0)
/* Power Management */
#define SYS_SCRATCH0 0xB1900018
#define SYS_SCRATCH1 0xB190001C
#define SYS_WAKEMSK 0xB1900034
#define SYS_ENDIAN 0xB1900038
#define SYS_POWERCTRL 0xB190003C
#define SYS_WAKESRC 0xB190005C
#define SYS_SLPPWR 0xB1900078
#define SYS_SLEEP 0xB190007C
/* Clock Controller */
#define SYS_FREQCTRL0 0xB1900020
#define SYS_FC_FRDIV2_BIT 22
#define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
#define SYS_FC_FE2 (1<<21)
#define SYS_FC_FS2 (1<<20)
#define SYS_FC_FRDIV1_BIT 12
#define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
#define SYS_FC_FE1 (1<<11)
#define SYS_FC_FS1 (1<<10)
#define SYS_FC_FRDIV0_BIT 2
#define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
#define SYS_FC_FE0 (1<<1)
#define SYS_FC_FS0 (1<<0)
#define SYS_FREQCTRL1 0xB1900024
#define SYS_FC_FRDIV5_BIT 22
#define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
#define SYS_FC_FE5 (1<<21)
#define SYS_FC_FS5 (1<<20)
#define SYS_FC_FRDIV4_BIT 12
#define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
#define SYS_FC_FE4 (1<<11)
#define SYS_FC_FS4 (1<<10)
#define SYS_FC_FRDIV3_BIT 2
#define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
#define SYS_FC_FE3 (1<<1)
#define SYS_FC_FS3 (1<<0)
#define SYS_CLKSRC 0xB1900028
#define SYS_CS_ME1_BIT 27
#define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT)
#define SYS_CS_DE1 (1<<26)
#define SYS_CS_CE1 (1<<25)
#define SYS_CS_ME0_BIT 22
#define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT)
#define SYS_CS_DE0 (1<<21)
#define SYS_CS_CE0 (1<<20)
#define SYS_CS_MI2_BIT 17
#define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT)
#define SYS_CS_DI2 (1<<16)
#define SYS_CS_CI2 (1<<15)
#define SYS_CS_MUH_BIT 12
#define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT)
#define SYS_CS_DUH (1<<11)
#define SYS_CS_CUH (1<<10)
#define SYS_CS_MUD_BIT 7
#define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT)
#define SYS_CS_DUD (1<<6)
#define SYS_CS_CUD (1<<5)
#define SYS_CS_MIR_BIT 2
#define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT)
#define SYS_CS_DIR (1<<1)
#define SYS_CS_CIR (1<<0)
#define SYS_CS_MUX_AUX 0x1
#define SYS_CS_MUX_FQ0 0x2
#define SYS_CS_MUX_FQ1 0x3
#define SYS_CS_MUX_FQ2 0x4
#define SYS_CS_MUX_FQ3 0x5
#define SYS_CS_MUX_FQ4 0x6
#define SYS_CS_MUX_FQ5 0x7
#define SYS_CPUPLL 0xB1900060
#define SYS_AUXPLL 0xB1900064
/* Secure Digital (SD) Controller */
#define SD0_XMIT_FIFO 0xB0600000
#define SD0_RECV_FIFO 0xB0600004
#define SD1_XMIT_FIFO 0xB0680000
#define SD1_RECV_FIFO 0xB0680004
/* Au1000 and Au1100 */
/* don't allow any legacy ports probing */
#define IOPORT_RESOURCE_START 0x10000000;
#define IOPORT_RESOURCE_END 0xffffffff
#define IOMEM_RESOURCE_START 0x10000000
#define IOMEM_RESOURCE_END 0xffffffff
#ifdef CONFIG_MIPS_PB1000
#define PCI_IO_START 0x10000000
#define PCI_IO_END 0x1000ffff
#define PCI_MEM_START 0x18000000
#define PCI_MEM_END 0x18ffffff
#define PCI_FIRST_DEVFN 0
#define PCI_LAST_DEVFN 1
#else
/* no PCI bus controller */
#define PCI_IO_START 0
#define PCI_IO_END 0
#define PCI_MEM_START 0
#define PCI_MEM_END 0
#define PCI_FIRST_DEVFN 0
#define PCI_LAST_DEVFN 0
#endif
/* Processor information base on prid.
* Copied from PowerPC.
*/
struct cpu_spec {
/* CPU is matched via (PRID & prid_mask) == prid_value */
unsigned int prid_mask;
unsigned int prid_value;
char *cpu_name;
unsigned char cpu_od; /* Set Config[OD] */
unsigned char cpu_bclk; /* Enable BCLK switching */
};
extern struct cpu_spec cpu_specs[];
extern struct cpu_spec *cur_cpu_spec[];
#endif
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