au1200.h

AU1200嵌入式处理器媒体加速引擎（mae）的驱动

/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Include file for Alchemy Semiconductor's Au1k CPU.
 *
 * Copyright 2000,2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	[e-mail] or [e-mail]
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

 /*
  * some definitions add by [e-mail] and [e-mail]
  */

#ifndef _AU1200_H_
#define _AU1200_H_


#ifndef _LANGUAGE_ASSEMBLY

#if 0
//jspjsp cpu pipeline flush 
void static inline au_sync(void)
{
	__asm__ volatile ("sync");
}

void static inline au_sync_udelay(int us)
{
	__asm__ volatile ("sync");
	udelay(us);
}

void static inline au_sync_delay(int ms)
{
	__asm__ volatile ("sync");
	mdelay(ms);
}
void static inline au_writeb(u8 val, int reg)
{
	*(volatile u8 *)(reg) = val;
}

void static inline au_writew(u16 val, int reg)
{
	*(volatile u16 *)(reg) = val;
}

void static inline au_writel(u32 val, int reg)
{
	*(volatile u32 *)(reg) = val;
}

static inline u8 au_readb(unsigned long port)
{
	return (*(volatile u8 *)port);
}

static inline u16 au_readw(unsigned long port)
{
	return (*(volatile u16 *)port);
}

static inline u32 au_readl(unsigned long port)
{
	return (*(volatile u32 *)port);
}
#endif

/* These next three functions should be a generic part of the MIPS
 * kernel (with the 'au_' removed from the name) and selected for
 * processors that support the instructions.
 * Taken from PPC tree.  -- Dan
 */
/* Return the bit position of the most significant 1 bit in a word */
// jspjsp 
#if 0
static __inline__ int __ilog2(unsigned int x)
{
	int lz;

	asm volatile (
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips32\n\t"
		"clz\t%0,%1\n\t"
		".set\tmips0\n\t"
		".set\tat\n\t"
		".set\treorder"
		: "=r" (lz)
		: "r" (x));

	return 31 - lz;
}

static __inline__ int au_ffz(unsigned int x)
{
	if ((x = ~x) == 0)
		return 32;
	return __ilog2(x & -x);
}

/*
 * ffs: find first bit set. This is defined the same way as
 * the libc and compiler builtin ffs routines, therefore
 * differs in spirit from the above ffz (man ffs).
 */
static __inline__ int au_ffs(int x)
{
	return __ilog2(x & -x) + 1;
}
#endif

/* arch/mips/au1000/common/clocks.c */
extern void set_au1x00_speed(unsigned int new_freq);
extern unsigned int get_au1x00_speed(void);
extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
extern unsigned long get_au1x00_uart_baud_base(void);
extern void set_au1x00_lcd_clock(void);
extern unsigned int get_au1x00_lcd_clock(void);

/*
 * Every board describes its IRQ mapping with this table.
 */
typedef struct au1xxx_irqmap {
	int	im_irq;
	int	im_type;
	int	im_request;
} au1xxx_irq_map_t;

/*
 * init_IRQ looks for a table with this name.
 */
extern au1xxx_irq_map_t au1xxx_irq_map[];

#endif /* !defined (_LANGUAGE_ASSEMBLY) */

#ifdef CONFIG_PM
/* no CP0 timer irq */
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
#else
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
#endif

/* Interrupt Controller 0 */
#define IC0_CFG0RD                 0xB0400040
#define IC0_CFG0SET                0xB0400040
#define IC0_CFG0CLR                0xB0400044

#define IC0_CFG1RD                 0xB0400048
#define IC0_CFG1SET                0xB0400048
#define IC0_CFG1CLR                0xB040004C

#define IC0_CFG2RD                 0xB0400050
#define IC0_CFG2SET                0xB0400050
#define IC0_CFG2CLR                0xB0400054

#define IC0_REQ0INT                0xB0400054
#define IC0_SRCRD                  0xB0400058
#define IC0_SRCSET                 0xB0400058
#define IC0_SRCCLR                 0xB040005C
#define IC0_REQ1INT                0xB040005C

#define IC0_ASSIGNRD               0xB0400060
#define IC0_ASSIGNSET              0xB0400060
#define IC0_ASSIGNCLR              0xB0400064

#define IC0_WAKERD                 0xB0400068
#define IC0_WAKESET                0xB0400068
#define IC0_WAKECLR                0xB040006C

#define IC0_MASKRD                 0xB0400070
#define IC0_MASKSET                0xB0400070
#define IC0_MASKCLR                0xB0400074

#define IC0_RISINGRD               0xB0400078
#define IC0_RISINGCLR              0xB0400078
#define IC0_FALLINGRD              0xB040007C
#define IC0_FALLINGCLR             0xB040007C

#define IC0_TESTBIT                0xB0400080

/* Interrupt Controller 1 */
#define IC1_CFG0RD                 0xB1800040
#define IC1_CFG0SET                0xB1800040
#define IC1_CFG0CLR                0xB1800044

#define IC1_CFG1RD                 0xB1800048
#define IC1_CFG1SET                0xB1800048
#define IC1_CFG1CLR                0xB180004C

#define IC1_CFG2RD                 0xB1800050
#define IC1_CFG2SET                0xB1800050
#define IC1_CFG2CLR                0xB1800054

#define IC1_REQ0INT                0xB1800054
#define IC1_SRCRD                  0xB1800058
#define IC1_SRCSET                 0xB1800058
#define IC1_SRCCLR                 0xB180005C
#define IC1_REQ1INT                0xB180005C

#define IC1_ASSIGNRD               0xB1800060
#define IC1_ASSIGNSET              0xB1800060
#define IC1_ASSIGNCLR              0xB1800064

#define IC1_WAKERD                 0xB1800068
#define IC1_WAKESET                0xB1800068
#define IC1_WAKECLR                0xB180006C

#define IC1_MASKRD                 0xB1800070
#define IC1_MASKSET                0xB1800070
#define IC1_MASKCLR                0xB1800074

#define IC1_RISINGRD               0xB1800078
#define IC1_RISINGCLR              0xB1800078
#define IC1_FALLINGRD              0xB180007C
#define IC1_FALLINGCLR             0xB180007C

#define IC1_TESTBIT                0xB1800080

/* Interrupt Configuration Modes */
#define INTC_INT_DISABLED                0
#define INTC_INT_RISE_EDGE             0x1
#define INTC_INT_FALL_EDGE             0x2
#define INTC_INT_RISE_AND_FALL_EDGE    0x3
#define INTC_INT_HIGH_LEVEL            0x5
#define INTC_INT_LOW_LEVEL             0x6
#define INTC_INT_HIGH_AND_LOW_LEVEL    0x7

/* Interrupt Numbers */


#ifdef CONFIG_SOC_AU1200
#define AU1200_UART0_INT          0
#define AU1200_SWT_INT            1
#define AU1200_SD_INT             2
#define AU1200_DDMA_INT           3
#define AU1200_MAE_BE_INT         4
#define AU1200_GPIO_200           5
#define AU1200_GPIO_201           6
#define AU1200_GPIO_202           7
#define AU1200_UART1_INT          8
#define AU1200_MAE_FE_INT         9
#define AU1200_PSC0_INT           10
#define AU1200_PSC1_INT           11
#define AU1200_AES_INT            12
#define AU1200_CAMERA_INT         13
#define AU1200_TOY_INT			  14
#define AU1200_TOY_MATCH0_INT     15