lcdgpe.cpp

AU1100嵌入式处理器lcd显示驱动程序

/*
 * File:	lcdgpe.c
 *
 * Purpose:	WinCE DDI utilizing GPE for Au1100 LCD controller
 *
 * NOTE:	This driver requires proper setup of cpu_auxpll in OEMInit()
 *
 * Author:	Alchemy Semiconductor
 * Date:	February 13, 2002
 */

//    Copyright (c) 2002-2004 BSQUARE Corporation.  All rights reserved.


#include "headers.h"

#define INSTANTIATE_MODE_TABLES
#define INSTANTIATE_PALETTE_TABLES

#include "registry.h"

static GPE *gpGPE = (GPE *)NULL;

static char gszCopyright[]="Copyright (C) Alchemy Semiconductor, Inc. 2002";

// The dpCurSettings structure
// ored in 0x10 to enable GPE_ZONE_ENTER - DEBUGZONE(4)
// ored in 0x200 to enable GPE_ZONE_FLIP - DEBUGZONE(9)
INSTANTIATE_GPE_ZONES(0x123,"DDI Driver","unused1","unused2")  /* Start with Errors, warnings, and temporary messages */

// RGB pixel layout used by LCD controller
BitMask RGB655 = { 0xFC00, 0x03E0, 0x001F };
BitMask RGB565 = { 0xF800, 0x07E0, 0x001F };
BitMask RGB556 = { 0xF800, 0x07C0, 0x003F };
BitMask RGB444 = { 0x0F00, 0x00F0, 0x000F };

/********************************************************************/
AU1100_LCD_MODE panels[] =
{
	{ /* 0 */
		TEXT("Pb1100 LCDA: Sharp 320x240 TFT panel, no rotate"),

	  	/* mode_control */
	   	( LCD_CONTROL_SBPPF_565
	   	/*LCD_CONTROL_WP*/
	   	/*LCD_CONTROL_WD*/
	   	| LCD_CONTROL_C
		| LCD_CONTROL_SM_0
	   	/*LCD_CONTROL_DB*/
	   	/*LCD_CONTROL_CCO*/
	   	/*LCD_CONTROL_DP*/
	   	| LCD_CONTROL_PO_00
		/*LCD_CONTROL_MPI*/
	   	| LCD_CONTROL_PT
	   	| LCD_CONTROL_PC
	   	| LCD_CONTROL_BPP_16 ),

		/* mode_horztiming */
		( LCD_HORZTIMING_HN2_N(8)
		| LCD_HORZTIMING_HN1_N(60)
		| LCD_HORZTIMING_HPW_N(12)
		| LCD_HORZTIMING_PPL_N(320) ),

		/* mode_verttiming */
		( LCD_VERTTIMING_VN2_N(5)
		| LCD_VERTTIMING_VN1_N(17)
		| LCD_VERTTIMING_VPW_N(1)
		| LCD_VERTTIMING_LPP_N(240) ),

		/* mode_clkcontrol */
		( 0
		/*LCD_CLKCONTROL_IB*/
		/*LCD_CLKCONTROL_IC*/
		/*LCD_CLKCONTROL_IH*/
		/*LCD_CLKCONTROL_IV*/
		| LCD_CLKCONTROL_PCD_N(1) ),

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		((1<<7) | (1<<6) | (1<<5)),

		/* mode_backlight */
		6,

		/* mode_bitmask */
		&RGB565
	},

	{ /* 1 */
		TEXT("Pb1100 LCDA: Sharp 320x240 TFT panel, rotated"),

	  	/* mode_control */
	   	( LCD_CONTROL_SBPPF_565
	   	/*LCD_CONTROL_WP*/
	   	/*LCD_CONTROL_WD*/
	   	| LCD_CONTROL_C
		| LCD_CONTROL_SM_90
	   	/*LCD_CONTROL_DB*/
	   	/*LCD_CONTROL_CCO*/
	   	/*LCD_CONTROL_DP*/
	   	| LCD_CONTROL_PO_00
		/*LCD_CONTROL_MPI*/
	   	| LCD_CONTROL_PT
	   	| LCD_CONTROL_PC
	   	| LCD_CONTROL_BPP_16 ),

		/* mode_horztiming */
		( LCD_HORZTIMING_HN2_N(8)
		| LCD_HORZTIMING_HN1_N(60)
		| LCD_HORZTIMING_HPW_N(12)
		| LCD_HORZTIMING_PPL_N(320) ),

		/* mode_verttiming */
		( LCD_VERTTIMING_VN2_N(5)
		| LCD_VERTTIMING_VN1_N(17)
		| LCD_VERTTIMING_VPW_N(1)
		| LCD_VERTTIMING_LPP_N(240) ),

		/* mode_clkcontrol */
		( 0
		/*LCD_CLKCONTROL_IB*/
		/*LCD_CLKCONTROL_IC*/
		/*LCD_CLKCONTROL_IH*/
		/*LCD_CLKCONTROL_IV*/
		| LCD_CLKCONTROL_PCD_N(1) ),

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		((1<<7) | (1<<6) | (1<<5)),

		/* mode_backlight */
		6,

		/* mode_bitmask */
		&RGB565
	},

	{ /* 2 */
		TEXT("Pb1100 LCDB: 640x480 PrimeView TFT panel"),

	  	/* mode_control */
	   	0x0004886a,

		/* mode_horztiming */
		0x0e4bfe7f,

		/* mode_verttiming */
		0x210805df,

		/* mode_clkcontrol */
		0x00038001,

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		((1<<7) | (1<<6) | (0<<5)),

		/* mode_backlight */
		7,

		/* mode_bitmask */
		&RGB565
	},

	{ /* 3 */
		TEXT("Pb1100 LCDC: 640x480 TFT panel, rotated 180"),

	  	/* mode_control */
//	   	0x004816a,

		// This works,  need to change pixel ordering when rotating.

	   	0x004c16a,

		/* mode_horztiming */
		0x3434d67f,

		/* mode_verttiming */
		0x0e0e39df,

		/* mode_clkcontrol */
		( 0
		/*LCD_CLKCONTROL_IB*/
		/*LCD_CLKCONTROL_IC*/
		/*LCD_CLKCONTROL_IH*/
		/*LCD_CLKCONTROL_IV*/
		| LCD_CLKCONTROL_PCD_N(1) ),

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		((1<<7) | (1<<6) | (0<<5)),

		/* mode_backlight */
		7,

		/* mode_bitmask */
		&RGB565
	},

	{ /* 4 */
		TEXT("Pb1100 NEON: 640x480x16bpp CRT, Hsync 30.7 kHz, Vsync 57.7 Hz"),

	  	/* mode_control */
	   	0x0004886A,

		// mode_horztiming
		// 15 pixels front porch
		// 76 pixels back porch
		// 64 pixels sync pulse
		0x1e3bfe7f,

		// mode_verttiming
		// 34 lines front porch
		// 9 lines back porch
		// 2 lines sync pulse
		0x210805df,

		/* mode_clkcontrol */
		// div to 24 MHz
		0x00020001,

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		// use 48 MHz clock
		((1<<7) | (1<<6) | (0<<5)),

		/* mode_backlight */
		7,

		/* mode_bitmask */
		&RGB565
	},
	{ /* 5 */
		TEXT("Pb1100 NEON: 800x600x16bpp CRT, Hsync 45.7 kHz, Vsync 68.7 Hz"),

	  	/* mode_control */
	   	0x0004886A,

		// mode_horztiming
		// 32 pixels front porch
		// 152 pixels back porch
		// 64 pixels sync pulse
		0x1F97FF1F,

		// mode_verttiming
		// 37 lines front porch
		// 23 lines back porch
		// 6 lines sync pulse
		0x24161A57,

		/* mode_clkcontrol */
		// keep at 47 MHz
		0x00020000,

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		// use 48 MHz clock
		((1<<7) | (1<<6) | (0<<5)),
		
		/* mode_backlight */
		7,

		/* mode_bitmask */
		&RGB565
	},
	{ /* 6 */
		TEXT("Pb1100 NEON: 640x480x16bpp CRT, HOG, Hsync 30.7 kHz, Vsync 57.7 Hz"),

	  	/* mode_control */
	   	0x0064886A,

		// mode_horztiming
		// 15 pixels front porch
		// 76 pixels back porch
		// 64 pixels sync pulse
		0x1e3bfe7f,

		// mode_verttiming
		// 34 lines front porch
		// 9 lines back porch
		// 2 lines sync pulse
		0x210805df,

		/* mode_clkcontrol */
		// div to 24 MHz
		0x00020001,

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		// use 48 MHz clock
		((1<<7) | (1<<6) | (0<<5)),

		/* mode_backlight */
		7,

		/* mode_bitmask */
		&RGB565
	},
	{ /* 7 */
		TEXT("Pb1100 NEON: 800x600x16bpp CRT, HOG, Hsync 45.7 kHz, Vsync 68.7 Hz"),

	  	/* mode_control */
	   	0x0064886A,

		// mode_horztiming
		// 32 pixels front porch
		// 152 pixels back porch
		// 64 pixels sync pulse
		0x1F97FF1F,

		// mode_verttiming
		// 37 lines front porch
		// 23 lines back porch
		// 6 lines sync pulse
		0x24161A57,

		/* mode_clkcontrol */
		// keep at 48 MHz
		0x00020000,

		/* mode_pwmdiv */
		0,

		/* mode_pwmhi */
		0,

		/* mode_toyclksrc */
		// use 48 MHz clock
		((1<<7) | (1<<6) | (0<<5)),
		
		/* mode_backlight */
		7,