2410配置fpga.txt

实现由ARM2410本身配置fpga的功能 fpga型号是ECP35和1K50/1C6

#include <string.h>
#include "def.h"
#include "2410addr.h"
#include "2410lib.h"
#include "spi.h"
#include "fpga.h"

// 1C6 和1C12  时序相同
#define spi_count1K50  (0x17eea+0x239ee)
//#define spi_count1C6  0x239ee   // 1c12-0x47000

volatile unsigned char *spiTxStr;
volatile unsigned char *spiTxStr1C6;
volatile int  endSpiTx;
volatile int endSpiTx1C6;
unsigned char *fpgabuff;
unsigned char *fpgabuff1C6;

void  Fpga_Cofig1(unsigned char DataFpga[], unsigned int sum)
{
	unsigned int  i=0, errorsum=0;
	unsigned char  k;
	unsigned char *ptrSdram, *ptrFpga1C6;
	unsigned char data;

	fpgabuff=(unsigned char *)0x31000000;            
	while(i < sum) 
	{
		k=DataFpga[i];           
		*fpgabuff++=((k&1)<<7)|((k&2)<<5)|((k&4)<<3)|((k&8)<<1)
			|((k&16)>>1)|((k&32)>>3)|((k&64)>>5)|((k&128)>>7);
		i++;
	}

	// verify config data 
	ptrSdram = (unsigned char *)0x31000000;     
	ptrFpga1C6 = (unsigned char *)fpga1C6;
	for (i=0; i<sum; i++)
	{
		k = *ptrSdram++;
		data = ((k&1)<<7)|((k&2)<<5)|((k&4)<<3)|((k&8)<<1)
			|((k&16)>>1)|((k&32)>>3)|((k&64)>>5)|((k&128)>>7);

		if ((*ptrFpga1C6++) != data)
		{
			errorsum++;
			Uart0_Printf("FPGA Config Data Error! \n\r");
			while(1);
		}
	}
	Uart0_Printf("FPGA Config Data ok! \n\r");
	
 }


void  SPI_Port_Init1(void)
{
	rGPEDAT=(rGPEDAT & (~(0x1<<11)))|(0x0<<11);//CFGD low
	rGPEDAT=(rGPEDAT & (~(0x1<<8))) |(0x0<<8);//NSTATUS low
	rGPEDAT=(rGPEDAT & (~(0x1<<7))) |(0x0<<7);//NCFG low

	rGPECON=(rGPECON & (~(0x3<<22))) | (0x0<<22); 	//GPE11 input
	rGPECON=(rGPECON & (~(0x3<<16))) | (0x0<<16);      //GPE8 input
	rGPECON=(rGPECON & (~(0x3<<14))) | (0x1<<14);      //GPE7 output

	rGPGCON=(rGPGCON & (~(0xf<<12))) | (0xf<<12); 	//GPG6   spiclk1
	
}

void spi_MS_poll1()
{
	unsigned int  i;
	int len;
   
	SPI_Port_Init1(); 
	
	while(rGPEDAT&(1<<8)); //NSTATUS LOW
	Delay(3000);
	rGPEDAT=rGPEDAT|(1<<7);  // NCFG HIGH
	Delay(3000);    
	while(!(rGPEDAT&(1<<8))); //NSTATUS HIGH
	Delay(3000);

	rSPPRE1=0x15;  // SPICLK1  
	rSPCON1=(0<<5)|(1<<4)|(1<<3)|(0<<2)|(0<<1)|(0<<0);//Polling,en-SCK,master,low,A,normal
	rSPPIN1=(0<<2)|(1<<1)|(0<<0);//dis-ENMUL,SBO,release

	// config 1k50
	//len=sizeof(fpga1C6)/sizeof(fpga1C6[0]);
	Fpga_Cofig1(fpga1C6, spi_count1K50);
	endSpiTx=0;	 
	spiTxStr=(unsigned char *)0x31000000;  	
	
	i=spi_count1K50;
	while(endSpiTx==0)
	{
	  	if(rSPSTA1 & 0x1)   //Check Tx ready state    
		{
			if(i > 0)  
				{rSPTDAT1=*spiTxStr++;  i--;}
			else  
				endSpiTx=1;
		}
	}
	
	// send 80 clock after configure
	i = 10;
	Delay(100);
	while(endSpiTx==0)
	{
	  	if(rSPSTA1 & 0x1)   //Check Tx ready state    
		{
			if(i > 0)  
				{rSPTDAT1=0;  i--;}
			else  
				endSpiTx=1;
		}		
	}

	//stop clock
	rSPCON1=(0<<5)|(0<<4)|(1<<3)|(1<<2)|(0<<1)|(0<<0);//Polling,dis-SCK,master,low,A,normal

}

void Fpga_init1()
{
	int i=25;
	int sum=0;
	unsigned char sign=0;
	endSpiTx=0;

	config:
	rGPEDAT = (rGPEDAT & (~(0x3<<9)))  | (0x2<<9); //灯亮
	spi_MS_poll1();	
	rGPEDAT = (rGPEDAT & (~(0x3<<9)))  | (0x1<<9);
	//while(!(rGPEDAT & (1<<11)));	//CFGD HIGH

	for(i=0; i<9000; i++)
	{
		if (rGPEDAT & (1<<11)) //CFGD HIGH
		{
			sign=1;
			break;
		}
	}
	if (sign!=1)  // configuration error
	{
		if (sum < 3)
		{
			Uart0_Printf("Config FPGA again!\n\r");
			sum++;
			goto config;
		}
		else
		{
			while(1);
			Uart0_Printf("Fail to config FPGA!\n\r");
		}
	}
	Uart0_Printf("config FPGA success!\n\r");
	rGPEDAT = (rGPEDAT & (~(0x3<<9)))  | (0x3<<9);
}

//----------------------------->

void  Fpga_Cofig2(unsigned char DataFpga[], unsigned int sum)
{
	unsigned int  i=0, errorsum=0;
	unsigned char  k;
	unsigned char *ptrSdram, *ptrFpga1C6;
	unsigned char data;

	fpgabuff=(unsigned char *)0x30e00000;            
	while(i < sum)  
	{
		//k=DataFpga[i];      
		*fpgabuff++=DataFpga[i];      
		//*fpgabuff++=((k&1)<<7)|((k&2)<<5)|((k&4)<<3)|((k&8)<<1)
		//	|((k&16)>>1)|((k&32)>>3)|((k&64)>>5)|((k&128)>>7);
		i++;
	}

	// verify config data 
	ptrSdram = (unsigned char *)0x30e00000;     
	ptrFpga1C6 = DataFpga;
	for (i=0; i<sum; i++)
	{
		data = *ptrSdram++;
		//k = *ptrSdram++;
		//data = ((k&1)<<7)|((k&2)<<5)|((k&4)<<3)|((k&8)<<1)
		//	|((k&16)>>1)|((k&32)>>3)|((k&64)>>5)|((k&128)>>7);

		if ((*ptrFpga1C6++) != data)
		{
			errorsum++;
			Uart0_Printf("FPGA Config Data Error! \n\r");
			while(1);
		}
	}
	Uart0_Printf("FPGA Config Data ok! \n\r");
	
 }


void  SPI_Port_Init2(void)
{
	rGPGDAT=(rGPGDAT & (~(0x1<<5)))|(0x1<<5);//CFGD low
	rGPCDAT=(rGPCDAT & (~(0x1<<5))) |(0x1<<5);//NSTATUS low  high
	rGPCDAT=(rGPCDAT & (~(0x1<<7))) |(0x0<<7);//NCFG low

	rGPGCON=(rGPGCON & (~(0x3<<10))) | (0x0<<10); 	//GPE11 input
	rGPCCON=(rGPCCON & (~(0x3<<10))) | (0x0<<10);      //GPE8 input  //测试拉高 
	rGPCCON=(rGPCCON & (~(0x3<<14))) | (0x1<<14);      //GPE7 output

	rGPECON=(rGPECON & (~(0xf<<24))) | (0xa<<24); 	//GPG6   spiclk0
}

void spi_MS_poll2()
{
	unsigned int  i;
	int len;
   
	SPI_Port_Init2(); 

	len = sizeof(fpga_m)/sizeof(fpga_m[0]);
	Fpga_Cofig2(fpga_m, len);
	endSpiTx=0;	 
	spiTxStr=(unsigned char *)0x30e00000;  	
	Delay(10000);
	if(rGPCDAT&(1<<5)) {}
	else {}
	//while(rGPCDAT&(1<<5)); //NSTATUS LOW
	Delay(3000);
	rGPCDAT=rGPCDAT|(1<<7);  // NCFG HIGH
	Delay(3000);    
	while(!(rGPCDAT&(1<<5))); //NSTATUS HIGH
	Delay(3000);

	rSPPRE0=0x15;  // SPICLK0  0x15
	rSPCON0=(0<<5)|(1<<4)|(1<<3)|(0<<2)|(0<<1)|(0<<0);//Polling,en-SCK,master,low,A,normal
	rSPPIN0=(0<<2)|(1<<1)|(0<<0);//dis-ENMUL,SBO,release

	// config 1k50
	
	i=len;
	while(endSpiTx==0)
	{
	  	if(rSPSTA0 & 0x1)   //Check Tx ready state    
		{
			if(i > 0)  
				{rSPTDAT0=*spiTxStr++;  i--;}
			else  
				endSpiTx=1;
		}
	}
	
	// send 80 clock after configure
	endSpiTx=0;
	i = 150;
	Delay(100);
	while(endSpiTx==0)
	{
	  	if(rSPSTA0 & 0x1)   //Check Tx ready state    
		{
			if(i > 0)  
				{rSPTDAT0=0;  i--;}
			else  
				endSpiTx=1;
		}		
	}

	//stop clock
	rSPCON0=(0<<5)|(0<<4)|(1<<3)|(1<<2)|(0<<1)|(0<<0);//Polling,dis-SCK,master,low,A,normal

}

void Fpga_init2()
{
	int i=25;
	int sum=0;
	unsigned char sign=0;
	unsigned char stringwrong[2][40]={{"Failed to configure the AnalogBoard!"},{"配置模拟板失败!"}};
	extern unsigned char Language;
	endSpiTx=0;

	config:
	rGPEDAT = (rGPEDAT & (~(0x3<<9)))  | (0x2<<9); //灯亮
	spi_MS_poll2();	
	rGPEDAT = (rGPEDAT & (~(0x3<<9)))  | (0x1<<9);
	//while(!(rGPEDAT & (1<<11)));	//CFGD HIGH

	for(i=0; i<9000; i++)
	{
		if (rGPGDAT & (1<<5)) //CFGD HIGH
		{
			sign=1;
			break;
		}
	}
	 while (sign!=1)  // configuration error
	{
		Glib_FilledRectangle(HINTX, HINTY, IMAGEW, HINTY+20, 0);
		PutString(100, 500, stringwrong[Language], 1);
		Delay(1000000);
		Glib_FilledRectangle(HINTX, HINTY, IMAGEW, HINTY+20, 0);
		/*
		if (sum < 3)
		{
			Uart0_Printf("Config FPGA again!\n\r");
			sum++;
			goto config;
		}
		else
		{
			//while(1);
			Uart0_Printf("Fail to config FPGA!\n\r");
		}
		*/
	}
	Uart0_Printf("config FPGA success!\n\r");
	rGPEDAT = (rGPEDAT & (~(0x3<<9)))  | (0x3<<9);
}