📄 isr_init.c
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#include <cdefBF533.h>
#include "sysreg.h"
#include "ccblkfn.h"
#include <sys\exception.h> //Interrupt Handling Header
#include <plx9054_bf533_test.h>
#include <signal.h> // for raise() function
//ReadMem AMS1 , 0X2010 0000 -- 0X2010 01FF;
extern unsigned short *pRead ;
//WriteMem AMS1 , 0X2010 0000 -- 0X2010 0FFF;
extern unsigned short *pWrite;
// Sdram 0x0000 0000 -- 0x0200 0000;
extern unsigned short *pSDRam;
// int to 9054
extern unsigned short *pInt9054 ;
// Set Dsp Status to app
extern unsigned short *pDspStatus ;
// Control penfa regsiter
extern unsigned short *pPenfaReg;
// Parameter from pc
extern unsigned short Parameter[PARAMETERMAXLENGTH];
int ParameterLength; // Parameter Length
int FreqSpeed; // Dsp run frequence speed
int Penfa; // Penfa value
Plx_dsp_com dsp2plx;
//////////////////////////////////////////////////////////
// parameter : Addr -- DMA Sdram Sdram Addr
// FPGA addr and the Length is static
//
//////////////////////////////////////////////////////////
extern void SdramDMAFPGA(unsigned long * Addr);
void plx9054_int(void)
{
*pInt9054 = 0xffff;
ssync();
*pInt9054 = 0x0000;
ssync();
}
//////////////////////////////////////////////////////////
// parameter : pCommand -- pc Command to FPGA
// return : The major function of Command
// not : The command which is has minor function will be done in the PF3 INT
/////////////////////////////////////////////////////////
int CommandCheck(unsigned short *pCommand)
{
switch(pCommand[0])
{
case 0x01:
{
if(pCommand[2] == 0x55 )
return START;
else if( pCommand[2] == 0xaa)
return STOP;
}break;
case 0x02:
{
if(pCommand[2] == 0x55 )
return TRANSSTART;
else if( pCommand[2] == 0xaa)
return TRANSSTOP ;
}break;
case 0x03:
{
return TRANSFER;
}
case 0x04:
{
return PENFATEST;
}
case 0x05:
{
return SPEEDCHANGE;
}
case 0x06:
{
if(pCommand[2] == 0xaa)
return RESETDSP;
}break;
case 0x07:
{
return DRIVER_READ_FPGA_OVER;
}
case 0x08:
{
return RETRY_DMA_SDRAM_TO_FPGA;
}
default :
return 0;
}// end switch
return 0;
}// end CommandCheck
///////////////////////////////////////////////////////////////////
// MDMA0 Int
///////////////////////////////////////////////////////////////////
EX_INTERRUPT_HANDLER(MDMA_INT)
{
ushort MDma_Status;
ushort tempL1ToSdramBank;
MDma_Status = *pMDMA_S1_IRQ_STATUS;
if(MDma_Status &0x0001)
{
*pDspStatus = 0x55aa; // Sdram to FPGA DMA over,set the DspStatus inform the app
// dsp2plx.SdramToFPGAOffset += FPGABUFFERLENGTH*2;
dsp2plx.SdramToFPGAOffset += FPGABUFFERLENGTH;
if(dsp2plx.SdramToFPGAOffset ==1024*1024*4*2)
{
dsp2plx.SdramToFPGAOffset = 0;
dsp2plx.SdramToFPGABank +=1;
if(dsp2plx.SdramToFPGABank >3)
{
dsp2plx.SdramToFPGABank = 0;
}
}
*pMDMA_S1_IRQ_STATUS = 0x1;
*pMDMA_D1_IRQ_STATUS = 0x1;
}
////////////////////////////////////////////////////////////////
MDma_Status = *pMDMA_S0_IRQ_STATUS;
if(MDma_Status&0x0001)
{
//dsp2plx.L1ToSdramOffset += FPGABUFFERLENGTH*2;
dsp2plx.L1ToSdramOffset += FPGABUFFERLENGTH;
if(dsp2plx.L1ToSdramOffset ==1024*1024*4*2)
{
dsp2plx.L1ToSdramOffset = 0;
tempL1ToSdramBank = dsp2plx.L1ToSdramBank;
tempL1ToSdramBank++;
if(tempL1ToSdramBank > 3)
tempL1ToSdramBank = 0;
// if L1ToSdramBank will conflict with SdramToFPGABank ,
// skip the SdramToFPGABank ,go ahead.
if(tempL1ToSdramBank == dsp2plx.SdramToFPGABank)
tempL1ToSdramBank++;
if(tempL1ToSdramBank > 3)
tempL1ToSdramBank = 0;
dsp2plx.L1ToSdramBank = tempL1ToSdramBank ;
}//end of if inner
*pMDMA_S0_IRQ_STATUS = 0x1;
*pMDMA_D0_IRQ_STATUS = 0x1;
}
}//end MDMA0
///////////////////////////////////////////////////////////////////
// DMA0 Int (PPI input)
///////////////////////////////////////////////////////////////////
EX_INTERRUPT_HANDLER(DMA0_INT)
{
ushort tempPpiToSdramBank;
// clear the DMA0_IRQ_STATUS
*pDMA0_IRQ_STATUS = 0x01;
if(dsp2plx.firtPpiInterrupt== 0)
dsp2plx.firtPpiInterrupt = 1;
dsp2plx.NumberCalculationbuf = dsp2plx.NumberOfPpibuf;
dsp2plx.NumberOfPpibuf ++;
if(dsp2plx.NumberOfPpibuf >=3)
dsp2plx.NumberOfPpibuf = 0;
}//end DMA0 (PPI input)
///////////////////////////////////////////////////////////////////
// DMA error Int
///////////////////////////////////////////////////////////////////
EX_INTERRUPT_HANDLER(DMA_ERR_DMA0_EER_INT)
{
ushort i;
i = *pPPI_STATUS ;
if((i>>12)&0x01)
{
StopPPI();
}
// *pPPI_STATUS &= ~(1<<12);
// StartPPI();
ushort Mdma_S0_Irq_Status,Mdma_D0_Irq_Status ;
*pMDMA_S0_CONFIG &= ~DMA_EN;
*pMDMA_D0_CONFIG &= ~DMA_EN;
Mdma_S0_Irq_Status = (*pMDMA_S0_IRQ_STATUS);
if(Mdma_S0_Irq_Status &0x02)
*pMDMA_S0_IRQ_STATUS = 0x02;
Mdma_D0_Irq_Status = (*pMDMA_D0_IRQ_STATUS);
if(Mdma_D0_Irq_Status &0x02)
*pMDMA_D0_IRQ_STATUS = 0x02;
// SdramDMAFPGA(dsp2plx.pSdramToFPGA+dsp2plx.SdramToFPGAOffset);
}
EX_INTERRUPT_HANDLER(DMA0_PPI_ISR) // <--|declaration in exception.h -->
{ // |declaration with _pragma(interrupt) the ISR Startaddress
//disable the interrupt request
*pDMA0_IRQ_STATUS = 0x1;
printf( "\nThe DMA0 PPI Interrupt has been entered!\n" );
}//end DMA0_PPI_ISR
int precom = 0,com = 0;
EX_INTERRUPT_HANDLER(PF3_INTA) // <--|declaration in exception.h -->
{ // |declaration with _pragma(interrupt) the ISR Startaddress
int i;
//disable the interrupt request
int pLength;
if( com !=TRANSFER) precom = com;
com = CommandCheck(pRead);
switch(com)
{
case START :
{
// Start PPI
StartPPI();
}break;
case STOP:
{
// Stop PPI
StopPPI();
}break;
case TRANSSTART:
{
ParameterLength = 0;
}break;
case TRANSFER:
{
if(precom == TRANSSTART)
{
pLength = pRead[1];
for( i = 0 ; i < pLength; i++)
{
Parameter[i+ParameterLength] = pRead[i+3];
}
ParameterLength += pLength;
}
}break;
case TRANSSTOP:
{
precom = 0;
}break;
case PENFATEST:
{
Penfa = pRead[3];
*pPenfaReg = Penfa;
}break;
case SPEEDCHANGE:
{
if(pRead[2] == 0x55)
{
FreqSpeed = pRead[3];
}
ushort freq = FreqSpeed;
ushort Msel,reg;
freq = (freq/15);
Msel = (ushort)freq;
*pPLL_CTL = 0x0001|((Msel)<<9);
reg = cli();
idle();
sti(reg);
}break;
case RESETDSP :
{
// raise(SIGRSET);
ushort status;
//*pSWRST |=0x0007;
// status = raise(SIGRSET);
}break;
case DRIVER_READ_FPGA_OVER:
{
*pDspStatus = 0;
// if(dsp2plx.SdramToFPGABank != dsp2plx.PpiToSdramBank)
{
dsp2plx.pSdramToFPGA = (ulong)(pSDRam+1024*1024*4*dsp2plx.SdramToFPGABank);
SdramDMAFPGA(dsp2plx.pSdramToFPGA+dsp2plx.SdramToFPGAOffset);
}
}break;
case RETRY_DMA_SDRAM_TO_FPGA:
{
//*pDspStatus = 0;
// if(dsp2plx.SdramToFPGABank != dsp2plx.PpiToSdramBank)
{
SdramDMAFPGA(dsp2plx.pSdramToFPGA+dsp2plx.SdramToFPGAOffset);
}
}
default: break;
}
i = *pFIO_FLAG_D ;//= 0X0008;//Clear the interrupt.
*pFIO_FLAG_C = 0X0008;
*pFIO_MASKA_C = 0x0008;
*pFIO_MASKA_S = 0x0008;
ssync();
//plx9054_int();
}//end PF2_INTA
void initPFLAGS(void)
{
*pFIO_DIR = 0x0000; // 0 set PF as input
*pFIO_POLAR = 0X00;
*pFIO_BOTH = 0X000;
*pFIO_MASKA_S = 0X0008;
*pFIO_MASKA_D = 0X0008;
*pFIO_EDGE = 0X0000;
*pFIO_INEN = 0x0008;// Enable PF3 as input
}
void Init_Interrupts(void)
{
// configure interrupt
/* *pSIC_IAR0 = *pSIC_IAR0 & 0xffffffff | 0x00000000;
*pSIC_IAR1 = *pSIC_IAR1 & 0xffffffff | 0x00000001; // map DMA0 PPI Interrupt -> IVG8
*pSIC_IAR2 = *pSIC_IAR2 & 0xffffffff | 0x00000000;
register_handler(ik_ivg8, DMA0_PPI_ISR); // assign DMA0 PPI ISR to interrupt vector 8
*/
// int pf3
register_handler(ik_ivg12, PF3_INTA);
// MDMA0
register_handler(ik_ivg13,MDMA_INT);
// DMA error Int & DMA0 Int
register_handler(ik_ivg7 ,DMA_ERR_DMA0_EER_INT);
//PPI error Int
register_handler(ik_ivg8 ,DMA0_INT);
*pSIC_IMASK = 0x00080100;
*pIMASK = 0X00001000;
// 0x00200000
*pSIC_IMASK |= (1<<21); // for MDMA0
*pSIC_IMASK |= (1<<22); // for MDMA1
// 0x00040000
*pIMASK |=(1<<13); // for ik_ivg13
//*pSIC_IMASK |= (1<<1); // fro DMA error
//*pIMASK |= (1<<7); //for ik_ivg7
*pSIC_IMASK |= (1<<8); // fro DMA0
*pIMASK |= (1<<8); //for ik_ivg8
//*pSIC_IMASK |= (1<<2); // fro PPI error
//*pIMASK |= (1<<7); //for ik_ivg7
}//end Init_Interrupts
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