ppi.c

基于adsp-bf533的异性纤维检测算法的实现

#include <cdefBF533.h>
#include "sysreg.h"
#include "ccblkfn.h"
#include <sys\exception.h>	
#include <plx9054_bf533_test.h>
extern Plx_dsp_com  dsp2plx;
// Sdram        0x0000 0000 -- 0x0200 0000;
extern unsigned short *pSDRam;
// Set Dsp Status to app
extern unsigned short *pDspStatus ;

DMA_DESC_PTR_LARGE Dma_desc_ptr_small[3];

void StartPPI();


void Init_PPI(void)
{

	//The PPI is set to receive 525 lines for each frame
	*pPPI_FRAME = 0;
	*pPPI_COUNT = FPGABUFFERLENGTH -1;
	*pPPI_DELAY = 0x0000;
	//*pPPI_CONTROL = 0x788c;	//PPI enabled, input mode, active video only, receive field 1&2, 
	                      //packing enabled, DMA32 enabled, skipping disabled, 8bit data bus, nothing inverted//	

	// input mode, active video only, receive field 1&2, 
	//packing enabled, DMA32 enabled, skipping disabled, 8bit data bus, nothing inverted
	//*pPPI_CONTROL =  FLD_SEL | PACK_EN | DMA32 | DLEN_8 ;
	*pPPI_CONTROL = 0x780c;	// input mode, active video only, receive field 1&2, 
	
	
	//*pDMA0_CONFIG =  WNR | WDSIZE_16 | DI_EN ;//| FLOW_1; 
	// Start address of data buffer
	//*pDMA0_START_ADDR = Ppibuf1//dsp2plx.PpiToSdramBank*4*1024*1024;
	// DMA inner loop count
	//*pDMA0_X_COUNT = FPGABUFFERLENGTH ;
	// Inner loop address increment
	//*pDMA0_X_MODIFY = 2;
	
	*pDMA0_PERIPHERAL_MAP  = 0x00;
	*pDMA0_CONFIG = 0x7900|WNR | WDSIZE_16 | DI_EN | RESTART;//stop mode,16-bit transfer,open DMA0 channel
	ssync();
	
	*pDMA0_NEXT_DESC_PTR   = &Dma_desc_ptr_small[0];
	*pDMA0_CONFIG|=DMA_EN;
	
//	StartPPI();
	

}//end Init_PPI

void StartPPI()
{
/*		*pDspStatus = 0;
 	dsp2plx.PpiToSdramBank = 0;
 	dsp2plx.pSdramToFPGA = (ulong)pSDRam;
 	dsp2plx.SdramToFPGAOffset = 0;
 	dsp2plx.SdramToFPGABank = 0;
 	 	
 	dsp2plx.pPpiToSdramAddr =0;
 	dsp2plx.L1ToSdramOffset = 0;
 	dsp2plx.NumberOfBuffer = 0;
 */	
 	

 	
 	*pPPI_CONTROL |=PORT_EN;
 	ssync();
}

void StopPPI()
{
	*pPPI_CONTROL &=~PORT_EN;
	ssync();
	*pDMA0_CONFIG   &=~DMA_EN;
	ssync();
	
}