register.h

基于adsp-bf533的异性纤维检测算法的实现

/*==================================================================================
// USB Registers (0xFFC0 4400 - 0xFFC0 47FF)
====================================================================================*/
#define USBD_ID_REG      (*(PVUS)(USBD_ID))     // USB Device ID Register
#define USBD_FRM_REG     (*(PVUS)(USBD_FRM))    // Current USB Frame Number
#define USBD_FRMAT_REG   (*(PVUS)(USBD_FRMAT))  // Match value for USB frame number.
#define USBD_EPBUF_REG   (*(PVUS)(USBD_EPBUF))  // Enables Download of Configuration Into UDC Core
#define USBD_STAT_REG    (*(PVUS)(USBD_STAT))   // Returns USBD Module Status
#define USBD_CTRL_REG    (*(PVUS)(USBD_CTRL))   // Allows Configuration and Control of USBD Module.
#define USBD_GINTR_REG   (*(PVUS)(USBD_GINTR))  // Global Interrupt Register
#define USBD_GMASK_REG   (*(PVUS)(USBD_GMASK))  // Global Interrupt Register Mask
#define USBD_DMACFG_REG  (*(PVUS)(USBD_DMACFG)) // DMA Master Channel Configuration Register
#define USBD_DMABL_REG   (*(PVUS)(USBD_DMABL))  // DMA Master Channel Base Address, Low
#define USBD_DMABH_REG   (*(PVUS)(USBD_DMABH))  // DMA Master Channel Base Address, High
#define USBD_DMACT_REG   (*(PVUS)(USBD_DMACT))  // DMA Master Channel Count Register
#define USBD_DMAIRQ_REG  (*(PVUS)(USBD_DMAIRQ)) // DMA Master Channel DMA Count Register
#define USBD_INTR0_REG   (*(PVUS)(USBD_INTR0))  // USB Endpoint 0 Interrupt Register
#define USBD_MASK0_REG   (*(PVUS)(USBD_MASK0))  // USB Endpoint 0 Mask Register
#define USBD_EPCFG0_REG  (*(PVUS)(USBD_EPCFG0)) // USB Endpoint 0 Control Register
#define USBD_EPADR0_REG  (*(PVUS)(USBD_EPADR0)) // USB Endpoint 0 Address Offset Register
#define USBD_EPLEN0_REG  (*(PVUS)(USBD_EPLEN0)) // USB Endpoint 0 Buffer Length Register
#define USBD_INTR1_REG   (*(PVUS)(USBD_INTR1))  // USB Endpoint 1 Interrupt Register
#define USBD_MASK1_REG   (*(PVUS)(USBD_MASK1))  // USB Endpoint 1 Mask Register
#define USBD_EPCFG1_REG  (*(PVUS)(USBD_EPCFG1)) // USB Endpoint 1 Control Register
#define USBD_EPADR1_REG  (*(PVUS)(USBD_EPADR1)) // USB Endpoint 1 Address Offset Register
#define USBD_EPLEN1_REG  (*(PVUS)(USBD_EPLEN1)) // USB Endpoint 1 Buffer Length Register
#define USBD_INTR2_REG   (*(PVUS)(USBD_INTR2))  // USB Endpoint 2 Interrupt Register
#define USBD_MASK2_REG   (*(PVUS)(USBD_MASK2))  // USB Endpoint 2 Mask Register
#define USBD_EPCFG2_REG  (*(PVUS)(USBD_EPCFG2)) // USB Endpoint 2 Control Register
#define USBD_EPADR2_REG  (*(PVUS)(USBD_EPADR2)) // USB Endpoint 2 Address Offset Register
#define USBD_EPLEN2_REG  (*(PVUS)(USBD_EPLEN2)) // USB Endpoint 2 Buffer Length Register
#define USBD_INTR3_REG   (*(PVUS)(USBD_INTR3))  // USB Endpoint 3 Interrupt Register
#define USBD_MASK3_REG   (*(PVUS)(USBD_MASK3))  // USB Endpoint 3 Mask Register
#define USBD_EPCFG3_REG  (*(PVUS)(USBD_EPCFG3)) // USB Endpoint 3 Control Register
#define USBD_EPADR3_REG  (*(PVUS)(USBD_EPADR3)) // USB Endpoint 3 Address Offset Register
#define USBD_EPLEN3_REG  (*(PVUS)(USBD_EPLEN3)) // USB Endpoint 3 Buffer Length Register
#define USBD_INTR4_REG   (*(PVUS)(USBD_INTR4))  // USB Endpoint 4 Interrupt Register
#define USBD_MASK4_REG   (*(PVUS)(USBD_MASK4))  // USB Endpoint 4 Mask Register
#define USBD_EPCFG4_REG  (*(PVUS)(USBD_EPCFG4)) // USB Endpoint 4 Control Register
#define USBD_EPADR4_REG  (*(PVUS)(USBD_EPADR4)) // USB Endpoint 4 Address Offset Register
#define USBD_EPLEN4_REG  (*(PVUS)(USBD_EPLEN4)) // USB Endpoint 4 Buffer Length Register
#define USBD_INTR5_REG   (*(PVUS)(USBD_INTR5))  // USB Endpoint 5 Interrupt Register
#define USBD_MASK5_REG   (*(PVUS)(USBD_MASK5))  // USB Endpoint 5 Mask Register
#define USBD_EPCFG5_REG  (*(PVUS)(USBD_EPCFG5)) // USB Endpoint 5 Control Register
#define USBD_EPADR5_REG  (*(PVUS)(USBD_EPADR5)) // USB Endpoint 5 Address Offset Register
#define USBD_EPLEN5_REG  (*(PVUS)(USBD_EPLEN5)) // USB Endpoint 5 Buffer Length Register
#define USBD_INTR6_REG   (*(PVUS)(USBD_INTR6))  // USB Endpoint 6 Interrupt Register
#define USBD_MASK6_REG   (*(PVUS)(USBD_MASK6))  // USB Endpoint 6 Mask Register
#define USBD_EPCFG6_REG  (*(PVUS)(USBD_EPCFG6)) // USB Endpoint 6 Control Register
#define USBD_EPADR6_REG  (*(PVUS)(USBD_EPADR6)) // USB Endpoint 6 Address Offset Register
#define USBD_EPLEN6_REG  (*(PVUS)(USBD_EPLEN6)) // USB Endpoint 6 Buffer Length Register
#define USBD_INTR7_REG   (*(PVUS)(USBD_INTR7))  // USB Endpoint 7 Interrupt Register
#define USBD_MASK7_REG   (*(PVUS)(USBD_MASK7))  // USB Endpoint 7 Mask Register
#define USBD_EPCFG7_REG  (*(PVUS)(USBD_EPCFG7)) // USB Endpoint 7 Control Register
#define USBD_EPADR7_REG  (*(PVUS)(USBD_EPADR7)) // USB Endpoint 7 Address Offset Register
#define USBD_EPLEN7_REG  (*(PVUS)(USBD_EPLEN7)) // USB Endpoint 7 Buffer Length Register

/*==================================================================================
// System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF)
====================================================================================*/
#define L1SBAR_REG    (*(PVUL)(L1SBAR))   // L1 SRAM Base Address Register
#define L1CSR_REG     (*(PVUL)(L1CSR))    // L1 SRAM Control Initialization Register
#define DB_NDBP_REG   (*(PVUL)(DB_NDBP))  // Next Descriptor Base Pointer
#define DB_ACOMP_REG  (*(PVUL)(DB_ACOMP)) // DMA Bus Address Comparator
#define DB_CCOMP_REG  (*(PVUL)(DB_CCOMP)) // DMA Bus Control Comparator

/*==================================================================================
// SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF)
====================================================================================*/
#define EBIU_SDGCTL_REG (*(PVUL)(EBIU_SDGCTL)) // SDRAM Global Control Register
#define EBIU_SDBCTL_REG (*(PVUL)(EBIU_SDBCTL)) // SDRAM Bank Control Register
#define EBIU_SDRRC_REG  (*(PVUL)(EBIU_SDRRC))  // SDRAM Refresh Rate Control Register
#define EBIU_SDSTAT_REG (*(PVUL)(EBIU_SDSTAT)) // SDRAM Status Register

/*==================================================================================
// Event/Interrupt Registers
====================================================================================*/
#define EVT0_REG		  (*(PVUL)(EVT0))  // Event Vector 0 ESR Address
#define EVT1_REG          (*(PVUL)(EVT1))  // Event Vector 1 ESR Address
#define EVT2_REG          (*(PVUL)(EVT2))  // Event Vector 2 ESR Address
#define EVT3_REG          (*(PVUL)(EVT3))  // Event Vector 3 ESR Address
#define EVT4_REG          (*(PVUL)(EVT4))  // Event Vector 4 ESR Address
#define EVT5_REG          (*(PVUL)(EVT5))  // Event Vector 5 ESR Address
#define EVT6_REG          (*(PVUL)(EVT6))  // Event Vector 6 ESR Address
#define EVT7_REG          (*(PVUL)(EVT7))  // Event Vector 7 ESR Address
#define EVT8_REG          (*(PVUL)(EVT8))  // Event Vector 8 ESR Address
#define EVT9_REG          (*(PVUL)(EVT9))  // Event Vector 9 ESR Address
#define EVT10_REG         (*(PVUL)(EVT10)) // Event Vector 10 ESR Address
#define EVT11_REG         (*(PVUL)(EVT11)) // Event Vector 11 ESR Address
#define EVT12_REG         (*(PVUL)(EVT12)) // Event Vector 12 ESR Address
#define EVT13_REG         (*(PVUL)(EVT13)) // Event Vector 13 ESR Address
#define EVT14_REG         (*(PVUL)(EVT14)) // Event Vector 14 ESR Address
#define EVT15_REG         (*(PVUL)(EVT15)) // Event Vector 15 ESR Address
#define EVT_OVERRIDE_REG  (*(PVUL)(EVT_OVERRIDE))// Event Vector Table Override Register
#define IMASK_REG         (*(PVUL)(IMASK)) // Interrupt Mask Register
#define IPEND_REG         (*(PVUL)(IPEND)) // Interrupt Pending Register
#define ILAT_REG          (*(PVUL)(ILAT))  // Interrupt Latch Register

/*==================================================================================
// Core Timer Registers
====================================================================================*/
#define TCNTL_REG    (*(PVUL)(TCNTL))    // Core Timer Control Register
#define TPERIOD_REG  (*(PVUL)(TPERIOD))  // Core Timer Period Register
#define TSCALE_REG   (*(PVUL)(TSCALE))   // Core Timer Scale Register
#define TCOUNT_REG   (*(PVUL)(TCOUNT))   // Core Timer Count Register

/*==================================================================================
// Debug/MP/Emulation Registers
====================================================================================*/
#define DSPID_REG    (*(PVUL)(DSPID))    // DSP Processor ID Register for MP implementations
#define DBGCTL_REG   (*(PVUL)(DBGCTL))   // Debug Control Register
#define DBGSTAT_REG  (*(PVUL)(DBGSTAT))  // Debug Status Register
#define EMUDAT_REG   (*(PVUL)(EMUDAT))   // Emulator Data Register

/*==================================================================================
// Trace Buffer Registers
====================================================================================*/
#define TBUFCTL_REG   (*(PVUL)(TBUFCTL))   // Trace Buffer Control Register
#define TBUFSTAT_REG  (*(PVUL)(TBUFSTAT))  // Trace Buffer Status Register
#define TBUF_REG      (*(PVUL)(TBUF))      // Trace Buffer

/*==================================================================================
// Watch Point Control Registers
====================================================================================*/
#define WPIACTL_REG    (*(PVUL)(WPIACTL))  // Instruction Watch Point Control Register
#define WPIA0_REG      (*(PVUL)(WPIA0))    // Instruction Watch Point Address 0
#define WPIA1_REG      (*(PVUL)(WPIA1))    // Instruction Watch Point Address 1
#define WPIA2_REG      (*(PVUL)(WPIA2))    // Instruction Watch Point Address 2
#define WPIA3_REG      (*(PVUL)(WPIA3))    // Instruction Watch Point Address 3
#define WPIA4_REG      (*(PVUL)(WPIA4))    // Instruction Watch Point Address 4
#define WPIA5_REG      (*(PVUL)(WPIA5))    // Instruction Watch Point Address 5
#define WPIACNT0_REG   (*(PVUL)(WPIACNT0)) // Instruction Watch Point Counter 0
#define WPIACNT1_REG   (*(PVUL)(WPIACNT1)) // Instruction Watch Point Counter 1
#define WPIACNT2_REG   (*(PVUL)(WPIACNT2)) // Instruction Watch Point Counter 2
#define WPIACNT3_REG   (*(PVUL)(WPIACNT3)) // Instruction Watch Point Counter 3
#define WPIACNT4_REG   (*(PVUL)(WPIACNT4)) // Instruction Watch Point Counter 4
#define WPIACNT5_REG   (*(PVUL)(WPIACNT5)) // Instruction Watch Point Counter 5
#define WPDACTL_REG    (*(PVUL)(WPDACTL))  // Data Watch Point Control Register
#define WPDA0_REG      (*(PVUL)(WPDA0))    // Data Watch Point Address 0
#define WPDA1_REG      (*(PVUL)(WPDA1))    // Data Watch Point Address 1
#define WPDACNT0_REG   (*(PVUL)(WPDACNT0)) // Data Watch Point Counter 0
#define WPDACNT1_REG   (*(PVUL)(WPDACNT1)) // Data Watch Point Counter 1
#define WPSTAT_REG     (*(PVUL)(WPSTAT))   // Watch Point Status Register

/*==================================================================================
// Performance Monitor Registers
====================================================================================*/
#define PFCTL_REG     (*(PVUL)(PFCTL))    // Performance Monitor Control Register
#define PFCNTR0_REG   (*(PVUL)(PFCNTR0))  // Performance Monitor Counter Register 0
#define PFCNTR1_REG   (*(PVUL)(PFCNTR1))  // Performance Monitor Counter Register 1




//===============================================================================
/*
// setup the General purpose register first !
#define FIO_DIR_REG		(*(PVUS)(FIO_DIR))
#define FIO_FLAG_S_REG	(*(PVUS)(FIO_FLAG_S))
#define FIO_FLAG_C_REG	(*(PVUS)(FIO_FLAG_C))

// setup the timer register 
#define TPERIOD_REG (*(PVUL)(TPERIOD))
#define TSCALE_REG  (*(PVUL)(TSCALE))
#define TCOUNT_REG  (*(PVUL)(TCOUNT))
#define TCNTL_REG	(*(PVUL)(TCNTL))

// setup interrupt mask register
#define IMASK_REG	(*(PVUL)(IMASK))
#define IPEND_REG	(*(PVUL)(IPEND))
#define ILAT_REG	(*(PVUL)(ILAT))
*/








#endif