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📄 pll_nonlinear.mdl

📁 课程设计做的PLL
💻 MDL
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	      X0		      "1"	      InheritSampleTime	      on	    }	    Block {	      BlockType		      Mux	      Name		      "Mux"	      Ports		      [3, 1, 0, 0, 0]	      Position		      [90, 44, 95, 166]	      Inputs		      "3"	    }	    Block {	      BlockType		      Terminator	      Name		      "Terminator"	      Position		      [260, 115, 280, 135]	    }	    Block {	      BlockType		      Outport	      Name		      "q"	      Position		      [260, 70, 280, 90]	      Port		      "1"	      OutputWhenDisabled      held	      InitialOutput	      "0"	    }	    Line {	      SrcBlock		      "Demux"	      SrcPort		      2	      DstBlock		      "Terminator"	      DstPort		      1	    }	    Line {	      SrcBlock		      "Demux"	      SrcPort		      1	      Points		      [25, 0]	      Branch {		DstBlock		"q"		DstPort			1	      }	      Branch {		Points			[0, -50]		DstBlock		"Memory"		DstPort			1	      }	    }	    Line {	      SrcBlock		      "Memory"	      SrcPort		      1	      Points		      [-50, 0; 0, 35]	      DstBlock		      "Mux"	      DstPort		      1	    }	    Line {	      SrcBlock		      "Logic"	      SrcPort		      1	      DstBlock		      "Demux"	      DstPort		      1	    }	    Line {	      SrcBlock		      "Mux"	      SrcPort		      1	      DstBlock		      "Logic"	      DstPort		      1	    }	    Line {	      SrcBlock		      "s"	      SrcPort		      1	      DstBlock		      "Mux"	      DstPort		      3	    }	    Line {	      SrcBlock		      "r"	      SrcPort		      1	      DstBlock		      "Mux"	      DstPort		      2	    }	  }	}	Block {	  BlockType		  SubSystem	  Name			  "SR2"	  Ports			  [2, 1, 0, 0, 0]	  Position		  [220, 177, 255, 248]	  ShowPortLabels	  on	  System {	    Name		    "SR2"	    Location		    [327, 450, 837, 657]	    Open		    off	    ToolBar		    off	    StatusBar		    off	    ScreenColor		    white	    PaperOrientation	    landscape	    PaperPositionMode	    auto	    PaperType		    usletter	    PaperUnits		    inches	    Block {	      BlockType		      Inport	      Name		      "s"	      Position		      [30, 95, 50, 115]	      Port		      "1"	      PortWidth		      "-1"	      SampleTime	      "-1"	    }	    Block {	      BlockType		      Inport	      Name		      "r"	      Position		      [30, 135, 50, 155]	      Port		      "2"	      PortWidth		      "-1"	      SampleTime	      "-1"	    }	    Block {	      BlockType		      Demux	      Name		      "Demux"	      Ports		      [1, 2, 0, 0, 0]	      Position		      [175, 56, 180, 149]	      Outputs		      "2"	    }	    Block {	      BlockType		      CombinatorialLogic	      Name		      "Logic"	      Position		      [115, 89, 145, 121]	      TruthTable	      "[0 1;0 1;1 0;0 1;1 0;0 1;1 0;1 0]"	    }	    Block {	      BlockType		      Memory	      Name		      "Memory"	      Position		      [115, 15, 155, 45]	      Orientation	      left	      X0		      "1"	      InheritSampleTime	      on	    }	    Block {	      BlockType		      Mux	      Name		      "Mux"	      Ports		      [3, 1, 0, 0, 0]	      Position		      [90, 44, 95, 166]	      Inputs		      "3"	    }	    Block {	      BlockType		      Terminator	      Name		      "Terminator"	      Position		      [260, 115, 280, 135]	    }	    Block {	      BlockType		      Outport	      Name		      "q"	      Position		      [260, 70, 280, 90]	      Port		      "1"	      OutputWhenDisabled      held	      InitialOutput	      "0"	    }	    Line {	      SrcBlock		      "Mux"	      SrcPort		      1	      DstBlock		      "Logic"	      DstPort		      1	    }	    Line {	      SrcBlock		      "Logic"	      SrcPort		      1	      DstBlock		      "Demux"	      DstPort		      1	    }	    Line {	      SrcBlock		      "Memory"	      SrcPort		      1	      Points		      [-50, 0; 0, 35]	      DstBlock		      "Mux"	      DstPort		      1	    }	    Line {	      SrcBlock		      "s"	      SrcPort		      1	      DstBlock		      "Mux"	      DstPort		      2	    }	    Line {	      SrcBlock		      "r"	      SrcPort		      1	      DstBlock		      "Mux"	      DstPort		      3	    }	    Line {	      SrcBlock		      "Demux"	      SrcPort		      1	      Points		      [25, 0]	      Branch {		Points			[0, -50]		DstBlock		"Memory"		DstPort			1	      }	      Branch {		DstBlock		"q"		DstPort			1	      }	    }	    Line {	      SrcBlock		      "Demux"	      SrcPort		      2	      DstBlock		      "Terminator"	      DstPort		      1	    }	  }	}	Block {	  BlockType		  ToWorkspace	  Name			  "To Workspace"	  Position		  [95, 130, 155, 160]	  VariableName		  "Kd"	  Buffer		  "1"	  Decimation		  "1"	  SampleTime		  "-1"	}	Block {	  BlockType		  Outport	  Name			  "PU"	  Position		  [635, 58, 665, 72]	  Port			  "1"	  OutputWhenDisabled	  held	  InitialOutput		  "[]"	}	Block {	  BlockType		  Outport	  Name			  "PD"	  Position		  [635, 253, 665, 267]	  Port			  "2"	  OutputWhenDisabled	  held	  InitialOutput		  "[]"	}	Line {	  SrcBlock		  "SR1"	  SrcPort		  1	  DstBlock		  "100ps2"	  DstPort		  1	}	Line {	  SrcBlock		  "NOR2"	  SrcPort		  1	  DstBlock		  "100ps3"	  DstPort		  1	}	Line {	  SrcBlock		  "100ps3"	  SrcPort		  1	  Points		  [10, 0]	  Branch {	    Points		    [0, -45; -470, 0]	    DstBlock		    "NOR1"	    DstPort		    1	  }	  Branch {	    DstBlock		    "PU"	    DstPort		    1	  }	}	Line {	  SrcBlock		  "SR2"	  SrcPort		  1	  DstBlock		  "100ps5"	  DstPort		  1	}	Line {	  SrcBlock		  "NOR5"	  SrcPort		  1	  DstBlock		  "100ps6"	  DstPort		  1	}	Line {	  SrcBlock		  "NOR3"	  SrcPort		  1	  DstBlock		  "100ps7"	  DstPort		  1	}	Line {	  SrcBlock		  "100ps7"	  SrcPort		  1	  Points		  [5, 0]	  Branch {	    Points		    [0, -30]	    Branch {	      Points		      [-135, 0; 0, 35; -105, 0]	      Branch {		DstBlock		"SR1"		DstPort			2	      }	      Branch {		DstBlock		"SR2"		DstPort			1	      }	    }	    Branch {	      DstBlock		      "NOR2"	      DstPort		      3	    }	  }	  Branch {	    DstBlock		    "NOR5"	    DstPort		    1	  }	}	Line {	  SrcBlock		  "100ps6"	  SrcPort		  1	  Points		  [15, 0]	  Branch {	    DstBlock		    "PD"	    DstPort		    1	  }	  Branch {	    Points		    [0, 45; -470, 0]	    DstBlock		    "NOR4"	    DstPort		    2	  }	}	Line {	  SrcBlock		  "NOR1"	  SrcPort		  1	  DstBlock		  "100ps1"	  DstPort		  1	}	Line {	  SrcBlock		  "NOR4"	  SrcPort		  1	  DstBlock		  "100ps4"	  DstPort		  1	}	Line {	  SrcBlock		  "Phase\nDetector\nGain"	  SrcPort		  1	  DstBlock		  "To Workspace"	  DstPort		  1	}	Line {	  SrcBlock		  "100ps2"	  SrcPort		  1	  Points		  [25, 0]	  Branch {	    Points		    [0, 45]	    DstBlock		    "NOR3"	    DstPort		    2	  }	  Branch {	    Points		    [0, -50]	    DstBlock		    "NOR2"	    DstPort		    2	  }	}	Line {	  SrcBlock		  "100ps1"	  SrcPort		  1	  Points		  [15, 0]	  Branch {	    DstBlock		    "SR1"	    DstPort		    1	  }	  Branch {	    Points		    [130, 0]	    Branch {	      DstBlock		      "NOR2"	      DstPort		      1	    }	    Branch {	      DstBlock		      "NOR3"	      DstPort		      1	    }	  }	}	Line {	  SrcBlock		  "Ref"	  SrcPort		  1	  DstBlock		  "NOR1"	  DstPort		  2	}	Line {	  SrcBlock		  "100ps5"	  SrcPort		  1	  Points		  [25, 0]	  Branch {	    Points		    [0, -45]	    DstBlock		    "NOR3"	    DstPort		    3	  }	  Branch {	    Points		    [0, 45]	    DstBlock		    "NOR5"	    DstPort		    2	  }	}	Line {	  SrcBlock		  "100ps4"	  SrcPort		  1	  Points		  [15, 0]	  Branch {	    DstBlock		    "SR2"	    DstPort		    2	  }	  Branch {	    Points		    [130, 0]	    Branch {	      DstBlock		      "NOR5"	      DstPort		      3	    }	    Branch {	      DstBlock		      "NOR3"	      DstPort		      4	    }	  }	}	Line {	  SrcBlock		  "Div"	  SrcPort		  1	  DstBlock		  "NOR4"	  DstPort		  1	}      }    }    Block {      BlockType		      ToWorkspace      Name		      "VCO tune"      Position		      [690, 56, 735, 74]      FontName		      "helvetica"      FontSize		      12      VariableName	      "vtune"      Buffer		      "1e6"      Decimation	      "1"      SampleTime	      "0"    }    Block {      BlockType		      ToWorkspace      Name		      "[Hz]"      Position		      [795, 118, 830, 132]      FontName		      "helvetica"      FontSize		      12      VariableName	      "fvco"      Buffer		      "1e6"      Decimation	      "1"      SampleTime	      "0"    }    Block {      BlockType		      Sum      Name		      "diff. to\nsingle"      Ports		      [2, 1, 0, 0, 0]      Position		      [335, 86, 355, 159]      Inputs		      "+-"    }    Block {      BlockType		      Constant      Name		      "divider modulus"      Position		      [570, 165, 590, 185]      Value		      "10"    }    Block {      BlockType		      DiscretePulseGenerator      Name		      "fref"      Position		      [110, 90, 140, 120]      Amplitude		      "1"      Period		      "2"      PulseWidth	      "1"      PhaseDelay	      "0"      SampleTime	      "1e-7/2"    }    Block {      BlockType		      TransferFcn      Name		      "integrator +\nphase lead"      Position		      [440, 107, 495, 143]      Numerator		      "[Tau2 1]"      Denominator	      "[Tau1 0]"    }    Block {      BlockType		      TransferFcn      Name		      "parasitic pole"      Position		      [540, 107, 595, 143]      Numerator		      "[1]"      Denominator	      "[Tau3 1]"    }    Block {      BlockType		      ToWorkspace      Name		      "pulses"      Position		      [795, 158, 830, 172]      FontName		      "helvetica"      FontSize		      12      VariableName	      "fdiv"      Buffer		      "1e6"      Decimation	      "1"      SampleTime	      "0"    }    Block {      BlockType		      SubSystem      Name		      "time"      Ports		      [0, 0, 0, 0, 0]      Position		      [107, 214, 153, 247]      FontName		      "helvetica"      FontSize		      12      ShowPortLabels	      off      MaskType		      "time"      MaskDisplay	      "disp('Save\\ntime t')"      MaskIconFrame	      on      MaskIconOpaque	      on      MaskIconRotate	      none      MaskIconUnits	      autoscale      System {	Name			"time"	Location		[163, 139, 498, 323]	Open			off	ToolBar			off	StatusBar		off	ScreenColor		white	PaperOrientation	landscape	PaperPositionMode	auto	PaperType		usletter	PaperUnits		inches	Block {	  BlockType		  Clock	  Name			  "Clock"	  Position		  [75, 105, 95, 125]	  DeleteFcn		  "simclock BlockIsBeingDestroyed"	  PostSaveFcn		  "simclock Save"	  Location		  [30, 40, 140, 75]	}	Block {	  BlockType		  ToWorkspace	  Name			  "To Workspace"	  Position		  [165, 107, 215, 123]	  VariableName		  "t"	  Buffer		  "1e6"	  Decimation		  "1"	  SampleTime		  "0"	}	Line {	  SrcBlock		  "Clock"	  SrcPort		  1	  DstBlock		  "To Workspace"	  DstPort		  1	}	Annotation {	  Position		  [147, 77]	  VerticalAlignment	  top	  Text			  "Save time vector t"	}      }    }    Line {      SrcBlock		      "divider modulus"      SrcPort		      1      Points		      [40, 0; 0, -30]      DstBlock		      "Abstarct VCO\nand Divider"      DstPort		      2    }    Line {      SrcBlock		      "Constant1"      SrcPort		      1      Points		      [60, 0]      DstBlock		      "Abstarct VCO\nand Divider"      DstPort		      3    }    Line {      SrcBlock		      "Abstarct VCO\nand Divider"      SrcPort		      3      Points		      [0, 0]      Branch {	DstBlock		"pulses"	DstPort			1      }      Branch {	Points			[0, 85; -535, 0]	DstBlock		"MC12040"	DstPort			2      }    }    Line {      SrcBlock		      "Abstarct VCO\nand Divider"      SrcPort		      1      DstBlock		      "[Hz]"      DstPort		      1    }    Line {      SrcBlock		      "MC12040"      SrcPort		      1      Points		      [10, 0]      Branch {	DstBlock		"diff. to\nsingle"	DstPort			1      }      Branch {	Points			[0, -50]	DstBlock		"3"	DstPort			1      }    }    Line {      SrcBlock		      "MC12040"      SrcPort		      2      Points		      [10, 0]      Branch {	DstBlock		"diff. to\nsingle"	DstPort			2      }      Branch {	Points			[0, 65]	DstBlock		"4"	DstPort			1      }    }    Line {      SrcBlock		      "fref"      SrcPort		      1      Points		      [45, 0]      Branch {	DstBlock		"MC12040"	DstPort			1      }      Branch {	Points			[0, -50]	DstBlock		"5"	DstPort			1      }    }    Line {      SrcBlock		      "integrator +\nphase lead"      SrcPort		      1      DstBlock		      "parasitic pole"      DstPort		      1    }    Line {      SrcBlock		      "parasitic pole"      SrcPort		      1      Points		      [40, 0]      Branch {	DstBlock		"Abstarct VCO\nand Divider"	DstPort			1      }      Branch {	Points			[0, -60]	DstBlock		"VCO tune"	DstPort			1      }    }    Line {      SrcBlock		      "diff. to\nsingle"      SrcPort		      1      Points		      [50, 0]      Branch {	DstBlock		"integrator +\nphase lead"	DstPort			1      }      Branch {	Points			[0, -70]	DstBlock		"6"	DstPort			1      }    }  }}

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