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<LI> Limited hold range=20
<LI> Reference feed-through=20
<LI> Gain compensation <BR> PLL parameter=20
adjustment</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 5: VCO's"></A>Lecture 5: VCO's</H3>
<UL>
<LI> A simple VCO=20
<LI> VCO specification sheets <BR> An improved =
VCO</LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 6: Dividers"></A>Lecture 6: Dividers</H3>
<UL>
<LI> Divider architectures=20
<LI> Divider noise <BR> ECL divider =
design</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 7: Phase/Frequency Detectors"></A>Lecture =
7:=20
Phase/Frequency Detectors</H3>
<UL>
<LI> Four quadrant multiplier=20
<LI> XOR gate=20
<LI> Edge triggered phase detector=20
<LI> PFD (frequency steering)=20
<LI> Sample/hold detector <BR> Non-linear =
effects</LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 8: Loop Filters"></A>Lecture 8: Loop =
Filters</H3>
<UL>
<LI> Integrator with phase lead correction=20
<LI> Op-amp limitations=20
<LI> Reference suppression=20
<LI> Systematic gain compensation=20
<LI> VCO pre-filter=20
<LI> Charge pumps <BR> Sources of =
noise</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 9: Sampled data Phase-Locked =
Loops"></A>Lecture 9:=20
Sampled data Phase-Locked Loops</H3>
<UL>
<LI> Sampling continuous signals=20
<LI> Sampling in the frequency domain=20
<LI> Discrete-time modelling with Z transforms=20
<LI> Sampled data phase-locked loops =
<BR> Discrete-time=20
modelling of a PLL</LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 10: Stability in Sampled Data =
PLL's"></A>Lecture 10:=20
Stability in Sampled Data PLL's</H3>
<UL>
<LI> Nyquist criterion for pseudo-continuous PLL's=20
<LI> Discrete-time PLL's <BR> Mixed discrete-time and=20
continuous-time PLL's</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 11: Phase Noise in Sampled Data =
PLL's"></A>Lecture=20
11: Phase Noise in Sampled Data PLL's</H3>
<UL>
<LI> Sampled data effects of divider, VCO, loop filter and=20
reference noise </LI></UL></TD>
<TD vAlign=3Dtop align=3Dleft NOSAVE>
<H3><A name=3D"Lecture 12: Transient Analysis"></A>Lecture 12: =
Transient=20
Analysis</H3>
<UL>
<LI> Z-transform=20
<LI> Simulink=20
<LI> Method from Crawford=20
<LI> Method from Van Paemel <BR> Method from=20
Madsen</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 13: Direct Digital Synthesis"></A>Lecture =
13: Direct=20
Digital Synthesis</H3>
<UL>
<LI> Basic architecture=20
<LI> Ideal output spectrum=20
<LI> Phase truncation=20
<LI> Finite lookup table word length=20
<LI> D/A non-linearity <BR> Time-domain=20
specifications</LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 14: Pulse Swallowing"></A>Lecture 14: Pulse =
Swallowing</H3>
<UL>
<LI> Indirect fractional-N synthesis=20
<LI> Dual/multi-modulus divider model =
<BR> Spurs</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 15: Phase Error Cancellation"></A>Lecture =
15: Phase=20
Error Cancellation</H3>
<UL>
<LI> Correcting before/after the phase detector=20
<LI> Effects of mismatch <BR> Before the =
DMD</LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 16: Hybrid Synthesizers"></A>Lecture 16: =
Hybrid=20
Synthesizers</H3>
<UL>
<LI> Multiple-loop PLL=20
<LI> PLL with DDS offset <BR> DDS driven =
PLL</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A=20
name=3D"Lecture 17: Noise Shaping in Fractional-N =
Synthesis"></A>Lecture 17:=20
Noise Shaping in Fractional-N Synthesis</H3>
<UL>
<LI> DS frequency synthesis=20
<LI> Divider modulus quantization=20
<LI> DS modulators <BR> DS modulator =
stability</LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A=20
name=3D"Lecture 18: Frequency Discriminator Based =
Synthesis"></A>Lecture 18:=20
Frequency Discriminator Based Synthesis</H3>
<UL>
<LI> Some points on fractional-N synthesis=20
<LI> DS frequency discriminator=20
<LI> Analytical DS frequency discriminator =
<BR> Another look=20
at the DSFD based synthesizer</LI></UL></TD></TR>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lecture 19: Continuous Phase =
Modulation"></A>Lecture 19:=20
Continuous Phase Modulation</H3>
<UL>
<LI> GMSK=20
<LI> Baseband I/Q with up-conversion <BR> Direct =
modulation=20
using fractional-N</LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A=20
name=3D"Lecture 20: Noise Reduction and Isolation =
Techniques"></A>Lecture=20
20: Noise Reduction and Isolation Techniques</H3>
<UL>
<LI> Grounding strategies=20
<BR> Shielding</LI></UL></TD></TR></TBODY></TABLE>
<CENTER>
<P><A name=3D"Laboratory exercises"></A><I><U><FONT size=3D+4>Laboratory =
exercises</FONT></U></I></CENTER>
<TABLE cols=3D3 width=3D"100%" border=3D1 NOSAVE>
<TBODY>
<TR NOSAVE>
<TD vAlign=3Dtop NOSAVE>
<H3><A=20
name=3D"Lab 1: Simple continuous-time PLL (Matlab + =
Simulink)"></A>Lab 1:=20
Simple continuous-time PLL (Matlab + Simulink)</H3>
<UL>
<LI> given linear model of PLL=20
<UL>
<LI> compute loop parameters </LI></UL>
<LI> simulate:=20
<UL>
<LI> open-loop response=20
<LI> Nyquist stability=20
<LI> transient response (frequency vs. time) </LI></UL>
<LI>Download the matlab files =20
<UL>
<LI><A =
href=3D"http://www.ee.oulu.fi/~hakki/lab1.ps">lab1.ps</A>(*)=20
<LI><A=20
=
href=3D"http://www.ee.oulu.fi/~hakki/lab1_param.m">lab1_param.m</A>=20
<LI><A=20
=
href=3D"http://www.ee.oulu.fi/~hakki/lab1_pllmodel.mdl">lab1_pllmodel.mdl=
</A>=20
</LI></UL></LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lab 2: Mixed-signal PLL (Simulink)"></A>Lab 2: =
Mixed-signal=20
PLL (Simulink)</H3>
<UL>
<LI> given non-linear PLL model with digital divider, PFD =
and=20
charge pump, simulate: </LI></UL>
<UL>
<UL>
<LI> acquisition (frequency steering)=20
<LI> effect of sampling (aliasing) </LI></UL>
<LI>Download the matlab files =20
<UL>
<LI><A =
href=3D"http://www.ee.oulu.fi/~hakki/lab2.ps">lab2.ps</A>=20
<LI><A=20
=
href=3D"http://www.ee.oulu.fi/~hakki/pll_nonlinear_param.m">pll_nonlinear=
_param.m</A>=20
<LI><A=20
=
href=3D"http://www.ee.oulu.fi/~hakki/pll_nonlinear.mdl">pll_nonlinear.mdl=
</A>=20
</LI></UL></LI></UL></TD>
<TD vAlign=3Dtop NOSAVE>
<H3><A name=3D"Lab 3: Phase noise in a sampled PLL =
(Matlab)"></A>Lab 3:=20
Phase noise in a sampled PLL (Matlab)</H3>
<UL>
<LI> given model of sampled PLL <BR> simulate output =
phase=20
noise from:</LI></UL>
<UL>
<UL>
<LI> resistor noise (thermal)=20
<LI> OP-AMP noise (voltage and current)=20
<LI> VCO phase noise=20
<LI> reference noise </LI></UL>
<LI>Download the matlab files=20
<UL>
<LI><A =
href=3D"http://www.ee.oulu.fi/~hakki/lab3.ps">lab3.ps</A>=20
<LI><A=20
=
href=3D"http://www.ee.oulu.fi/~hakki/pll_mod_param.m">pll_mod_param.m</A>=
=20
<LI><A =
href=3D"http://www.ee.oulu.fi/~hakki/pll_mod.mdl">pll_mod.mdl</A>=20
</LI></UL></LI></UL></TD></TR></TBODY></TABLE>(*)Please =
notice, that the=20
contents of the exercises don't necesarily match the pre-hand =
descriptions.=20
Check the respective PS-files for exercise details. <BR>
<HR width=3D"100%">
<BR><FONT color=3D#000000>For more information contact </FONT> <A=20
href=3D"mailto:hakki@ee.oulu.fi">mailto:hakki@ee.oulu.fi</A> <BR>For =
late=20
registration please contact <A=20
href=3D"mailto:juha@ee.oulu.fi">mailto:juha@ee.oulu.fi</A> <BR> =
<BR> =20
<BR><BR><BR><BR>
<CENTER>
<P>
<HR width=3D"100%">
<FONT size=3D-1>This page last updated on November 13, =
1998.</FONT></CENTER>
<CENTER>
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