workonebeta.map.rpt

Verilog实现的DDS正弦信号发生器和测频测相模块

; DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ALTSYNCRAM             ; AUTO ; ROM  ; 1024         ; 12           ; --           ; --           ; 12288 ; Sin_12b.mif ;
+-----------------------------------------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+-------+-------------+


+-------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                  ;
+----------------------------------------+--------------------------------------------+
; Register name                          ; Reason for Removal                         ;
+----------------------------------------+--------------------------------------------+
; MeasureU0/rPhaseClockCounter[0]        ; Merged with MeasureU0/rFreClockCounter[0]  ;
; ReadU0/SourceData[64]                  ; Merged with ReadU0/SourceData[0]           ;
; MeasureU0/rPhaseClockCounter[1]        ; Merged with MeasureU0/rFreClockCounter[1]  ;
; ReadU0/SourceData[1]                   ; Merged with ReadU0/SourceData[65]          ;
; MeasureU0/rPhaseClockCounter[2]        ; Merged with MeasureU0/rFreClockCounter[2]  ;
; ReadU0/SourceData[2]                   ; Merged with ReadU0/SourceData[66]          ;
; MeasureU0/rPhaseClockCounter[3]        ; Merged with MeasureU0/rFreClockCounter[3]  ;
; ReadU0/SourceData[3]                   ; Merged with ReadU0/SourceData[67]          ;
; MeasureU0/rPhaseClockCounter[4]        ; Merged with MeasureU0/rFreClockCounter[4]  ;
; ReadU0/SourceData[4]                   ; Merged with ReadU0/SourceData[68]          ;
; MeasureU0/rPhaseClockCounter[5]        ; Merged with MeasureU0/rFreClockCounter[5]  ;
; ReadU0/SourceData[5]                   ; Merged with ReadU0/SourceData[69]          ;
; MeasureU0/rPhaseClockCounter[6]        ; Merged with MeasureU0/rFreClockCounter[6]  ;
; ReadU0/SourceData[6]                   ; Merged with ReadU0/SourceData[70]          ;
; MeasureU0/rPhaseClockCounter[7]        ; Merged with MeasureU0/rFreClockCounter[7]  ;
; ReadU0/SourceData[7]                   ; Merged with ReadU0/SourceData[71]          ;
; MeasureU0/rPhaseClockCounter[8]        ; Merged with MeasureU0/rFreClockCounter[8]  ;
; ReadU0/SourceData[8]                   ; Merged with ReadU0/SourceData[72]          ;
; MeasureU0/rPhaseClockCounter[9]        ; Merged with MeasureU0/rFreClockCounter[9]  ;
; ReadU0/SourceData[9]                   ; Merged with ReadU0/SourceData[73]          ;
; MeasureU0/rPhaseClockCounter[10]       ; Merged with MeasureU0/rFreClockCounter[10] ;
; ReadU0/SourceData[10]                  ; Merged with ReadU0/SourceData[74]          ;
; MeasureU0/rPhaseClockCounter[11]       ; Merged with MeasureU0/rFreClockCounter[11] ;
; ReadU0/SourceData[11]                  ; Merged with ReadU0/SourceData[75]          ;
; MeasureU0/rPhaseClockCounter[12]       ; Merged with MeasureU0/rFreClockCounter[12] ;
; ReadU0/SourceData[12]                  ; Merged with ReadU0/SourceData[76]          ;
; MeasureU0/rPhaseClockCounter[13]       ; Merged with MeasureU0/rFreClockCounter[13] ;
; ReadU0/SourceData[13]                  ; Merged with ReadU0/SourceData[77]          ;
; MeasureU0/rPhaseClockCounter[14]       ; Merged with MeasureU0/rFreClockCounter[14] ;
; ReadU0/SourceData[14]                  ; Merged with ReadU0/SourceData[78]          ;
; MeasureU0/rPhaseClockCounter[15]       ; Merged with MeasureU0/rFreClockCounter[15] ;
; ReadU0/SourceData[15]                  ; Merged with ReadU0/SourceData[79]          ;
; MeasureU0/rPhaseClockCounter[16]       ; Merged with MeasureU0/rFreClockCounter[16] ;
; ReadU0/SourceData[16]                  ; Merged with ReadU0/SourceData[80]          ;
; MeasureU0/rPhaseClockCounter[17]       ; Merged with MeasureU0/rFreClockCounter[17] ;
; ReadU0/SourceData[17]                  ; Merged with ReadU0/SourceData[81]          ;
; MeasureU0/rPhaseClockCounter[18]       ; Merged with MeasureU0/rFreClockCounter[18] ;
; ReadU0/SourceData[18]                  ; Merged with ReadU0/SourceData[82]          ;
; MeasureU0/rPhaseClockCounter[19]       ; Merged with MeasureU0/rFreClockCounter[19] ;
; ReadU0/SourceData[19]                  ; Merged with ReadU0/SourceData[83]          ;
; MeasureU0/rPhaseClockCounter[20]       ; Merged with MeasureU0/rFreClockCounter[20] ;
; ReadU0/SourceData[20]                  ; Merged with ReadU0/SourceData[84]          ;
; MeasureU0/rPhaseClockCounter[21]       ; Merged with MeasureU0/rFreClockCounter[21] ;
; ReadU0/SourceData[21]                  ; Merged with ReadU0/SourceData[85]          ;
; MeasureU0/rPhaseClockCounter[22]       ; Merged with MeasureU0/rFreClockCounter[22] ;
; ReadU0/SourceData[22]                  ; Merged with ReadU0/SourceData[86]          ;
; MeasureU0/rPhaseClockCounter[23]       ; Merged with MeasureU0/rFreClockCounter[23] ;
; ReadU0/SourceData[23]                  ; Merged with ReadU0/SourceData[87]          ;
; MeasureU0/rPhaseClockCounter[24]       ; Merged with MeasureU0/rFreClockCounter[24] ;
; ReadU0/SourceData[24]                  ; Merged with ReadU0/SourceData[88]          ;
; MeasureU0/rPhaseClockCounter[25]       ; Merged with MeasureU0/rFreClockCounter[25] ;
; ReadU0/SourceData[25]                  ; Merged with ReadU0/SourceData[89]          ;
; MeasureU0/rPhaseClockCounter[26]       ; Merged with MeasureU0/rFreClockCounter[26] ;
; ReadU0/SourceData[26]                  ; Merged with ReadU0/SourceData[90]          ;
; MeasureU0/rPhaseClockCounter[27]       ; Merged with MeasureU0/rFreClockCounter[27] ;
; ReadU0/SourceData[27]                  ; Merged with ReadU0/SourceData[91]          ;
; MeasureU0/rPhaseClockCounter[28]       ; Merged with MeasureU0/rFreClockCounter[28] ;
; ReadU0/SourceData[28]                  ; Merged with ReadU0/SourceData[92]          ;
; MeasureU0/rPhaseClockCounter[29]       ; Merged with MeasureU0/rFreClockCounter[29] ;
; ReadU0/SourceData[29]                  ; Merged with ReadU0/SourceData[93]          ;
; MeasureU0/rPhaseClockCounter[30]       ; Merged with MeasureU0/rFreClockCounter[30] ;
; ReadU0/SourceData[30]                  ; Merged with ReadU0/SourceData[94]          ;
; MeasureU0/rPhaseClockCounter[31]       ; Merged with MeasureU0/rFreClockCounter[31] ;
; ReadU0/SourceData[31]                  ; Merged with ReadU0/SourceData[95]          ;
; Total Number of Removed Registers = 64 ;                                            ;
+----------------------------------------+--------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 315   ;
; Number of registers using Synchronous Clear  ; 56    ;
; Number of registers using Synchronous Load   ; 11    ;
; Number of registers using Asynchronous Clear ; 224   ;
; Number of registers using Asynchronous Load  ; 1     ;
; Number of registers using Clock Enable       ; 113   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; Read:ReadU0|rIndicatorLight            ; 1       ;
; Measure:MeasureU0|rIndicatorLight      ; 1       ;
; Adjust:AdjustU0|rSetFrequency[1]       ; 4       ;
; Adjust:AdjustU0|rSetFrequency[4]       ; 4       ;
; Adjust:AdjustU0|rSetFrequency[5]       ; 4       ;
; Adjust:AdjustU0|rSetPhase[1]           ; 4       ;
; Adjust:AdjustU0|rSetPhase[3]           ; 4       ;
; Adjust:AdjustU0|rSetPhase[4]           ; 4       ;
; Adjust:AdjustU0|rSetPhase[6]           ; 4       ;
; Total number of inverted registers = 9 ;         ;
+----------------------------------------+---------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; 8:1                ; 5 bits    ; 25 LEs        ; 10 LEs               ; 15 LEs                 ; Yes        ; |TopLayer|Adjust:AdjustU0|rSetFrequency[2] ;
; 8:1                ; 3 bits    ; 15 LEs        ; 6 LEs                ; 9 LEs                  ; Yes        ; |TopLayer|Adjust:AdjustU0|rSetPhase[7]     ;
; 8:1                ; 3 bits    ; 15 LEs        ; 6 LEs                ; 9 LEs                  ; Yes        ; |TopLayer|Adjust:AdjustU0|rSetFrequency[1] ;
; 8:1                ; 4 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; Yes        ; |TopLayer|Adjust:AdjustU0|rSetPhase[6]     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+