accumulater.v.bak

Verilog实现的DDS正弦信号发生器和测频测相模块

module Accumulater(Clock, Base, Increment);
input Clock;
output [29:0] Base;
input [21:0] Increment;

//wire Clock;
reg [29:0] Base;
wire [21:0] Increment;

//wire [31:0] temp;
//assign temp = Increment;

always @(posedge Clock)
begin
    Base <= Base + Increment;
end

endmodule