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Verilog实现的DDS正弦信号发生器和测频测相模块

Analysis & Synthesis Status : Successful - Tue Aug 21 22:08:24 2007
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : WorkOneBeta
Top-level Entity Name : TopLayer
Family : Cyclone
Total logic elements : 474
Total pins : 50
Total virtual pins : 0
Total memory bits : 51,718
Total PLLs : 0