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📄 workonebeta.vo

📁 Verilog实现的DDS正弦信号发生器和测频测相模块
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AND1 \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[4]pt_buf (
	.IN1(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]),
	.Y(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[4] ));

AND1 \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[5]pt_buf (
	.IN1(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]),
	.Y(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[5] ));

AND1 \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[6]pt_buf (
	.IN1(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]),
	.Y(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[6] ));

AND1 \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[7]pt_buf (
	.IN1(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]),
	.Y(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[7] ));

AND1 \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[8]pt_buf (
	.IN1(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8]),
	.Y(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[8] ));


AND1 \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[9]pt_buf (
	.IN1(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]),
	.Y(\AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a[9] ));


AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[17]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[17] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[16]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [1]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[16] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[15]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [2]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[15] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[14]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [3]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[14] ));


AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[13]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[13] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[12]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [1]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[12] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[11]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [2]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[11] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[10]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [3]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[10] ));


AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[9]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[9] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[8]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [1]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[8] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[7]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [2]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[7] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[6]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [3]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[6] ));


AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[5]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[5] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[4]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [1]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[4] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[3]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [2]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[3] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[2]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [3]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[2] ));


AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[1]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[1] ));

AND1 \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[0]pt_buf (
	.IN1(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [1]),
	.Y(\AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a[0] ));


INV \ReadU0|INV_INST_rIndicatorLight~regout  (
	.IN1(\ReadU0|rIndicatorLight~regout ),
	.Y(\ReadU0|ALT_INV_rIndicatorLight~regout ));

INV \MeasureU0|INV_INST_rIndicatorLight~regout  (
	.IN1(\MeasureU0|rIndicatorLight~regout ),
	.Y(\MeasureU0|ALT_INV_rIndicatorLight~regout ));

INV \INV_INST_Reset~combout  (
	.IN1(\Reset~combout ),
	.Y(\ALT_INV_Reset~combout ));

// atom is at LC_X24_Y6_N2
cyclone_lcell \MeasureU0|And (
// Equation(s):
// \MeasureU0|And~combout  = LCELL(\SysClock~combout  & (\WaveInOne~combout  $ \WaveInTwo~combout ))

	.clk(gnd),
	.dataa(vcc),
	.datab(\SysClock~combout ),
	.datac(\WaveInOne~combout ),
	.datad(\WaveInTwo~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.modesel(13'b1001001010101),
	.combout(\MeasureU0|And~combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1(),
	.pathsel(11'b00000001110));
// synopsys translate_off
// defparam \MeasureU0|And .lut_mask = "0cc0";
// defparam \MeasureU0|And .operation_mode = "normal";
// defparam \MeasureU0|And .output_mode = "comb_only";
// defparam \MeasureU0|And .register_cascade_mode = "off";
// defparam \MeasureU0|And .sum_lutc_input = "datac";
// defparam \MeasureU0|And .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_10
cyclone_io \ReadClock~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.modesel(27'b000000000000000000000000001),
	.combout(\ReadClock~combout ),
	.regout(),
	.padio(ReadClock));
// synopsys translate_off
// defparam \ReadClock~I .input_async_reset = "none";
// defparam \ReadClock~I .input_power_up = "low";
// defparam \ReadClock~I .input_register_mode = "none";
// defparam \ReadClock~I .input_sync_reset = "none";
// defparam \ReadClock~I .oe_async_reset = "none";
// defparam \ReadClock~I .oe_power_up = "low";
// defparam \ReadClock~I .oe_register_mode = "none";
// defparam \ReadClock~I .oe_sync_reset = "none";
// defparam \ReadClock~I .operation_mode = "input";
// defparam \ReadClock~I .output_async_reset = "none";
// defparam \ReadClock~I .output_power_up = "low";
// defparam \ReadClock~I .output_register_mode = "none";
// defparam \ReadClock~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_134
cyclone_io \Reset~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.modesel(27'b000000000000000000000000001),
	.combout(\Reset~combout ),
	.regout(),
	.padio(Reset));
// synopsys translate_off
// defparam \Reset~I .input_async_reset = "none";
// defparam \Reset~I .input_power_up = "low";
// defparam \Reset~I .input_register_mode = "none";
// defparam \Reset~I .input_sync_reset = "none";
// defparam \Reset~I .oe_async_reset = "none";
// defparam \Reset~I .oe_power_up = "low";
// defparam \Reset~I .oe_register_mode = "none";
// defparam \Reset~I .oe_sync_reset = "none";
// defparam \Reset~I .operation_mode = "input";
// defparam \Reset~I .output_async_reset = "none";
// defparam \Reset~I .output_power_up = "low";
// defparam \Reset~I .output_register_mode = "none";
// defparam \Reset~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X12_Y6_N6
cyclone_lcell \ReadU0|Counter[0] (
// Equation(s):
// \ReadU0|Counter[0]~regout  = DFFEAS(!\ReadU0|Counter[0]~regout , GLOBAL(\ReadClock~combout ), !GLOBAL(\Reset~combout ), , , , , , )

	.clk(\ReadClock~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\ReadU0|Counter[0]~regout ),
	.aclr(\Reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.modesel(13'b1100001010101),
	.combout(),
	.regout(\ReadU0|Counter[0]~regout ),
	.cout(),
	.cout0(),
	.cout1(),
	.pathsel(11'b00000001000));
// synopsys translate_off
// defparam \ReadU0|Counter[0] .lut_mask = "00ff";
// defparam \ReadU0|Counter[0] .operation_mode = "normal";
// defparam \ReadU0|Counter[0] .output_mode = "reg_only";
// defparam \ReadU0|Counter[0] .register_cascade_mode = "off";
// defparam \ReadU0|Counter[0] .sum_lutc_input = "datac";
// defparam \ReadU0|Counter[0] .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X16_Y3_N1
cyclone_lcell \ReadU0|Counter[1] (
// Equation(s):
// \ReadU0|Counter[1]~regout  = DFFEAS(\ReadU0|Counter[0]~regout  $ \ReadU0|Counter[1]~regout , GLOBAL(\ReadClock~combout ), !GLOBAL(\Reset~combout ), , , , , , )
// \ReadU0|Counter[1]~28  = CARRY(\ReadU0|Counter[0]~regout  & \ReadU0|Counter[1]~regout )
// \ReadU0|Counter[1]~28COUT1  = CARRY(\ReadU0|Counter[0]~regout  & \ReadU0|Counter[1]~regout )

	.clk(\ReadClock~combout ),
	.dataa(\ReadU0|Counter[0]~regout ),
	.datab(\ReadU0|Counter[1]~regout ),
	.datac(vcc),
	.datad(vcc),
	.aclr(\Reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.modesel(13'b1100001010110),
	.combout(),
	.regout(\ReadU0|Counter[1]~regout ),
	.cout(),
	.cout0(\ReadU0|Counter[1]~28 ),
	.cout1(\ReadU0|Counter[1]~28COUT1 ),
	.pathsel(11'b00110000011));
// synopsys translate_off
// defparam \ReadU0|Counter[1] .lut_mask = "6688";
// defparam \ReadU0|Counter[1] .operation_mode = "arithmetic";
// defparam \ReadU0|Counter[1] .output_mode = "reg_only";
// defparam \ReadU0|Counter[1] .register_cascade_mode = "off";
// defparam \ReadU0|Counter[1] .sum_lutc_input = "datac";
// defparam \ReadU0|Counter[1] .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X16_Y3_N2
cyclone_lcell \ReadU0|Counter[2] (
// Equation(s):
// \ReadU0|Counter[2]~regout  = DFFEAS(\ReadU0|Counter[2]~regout  $ (\ReadU0|Counter[1]~28 ), GLOBAL(\ReadClock~combout ), !GLOBAL(
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