workonebeta.vo

Verilog实现的DDS正弦信号发生器和测频测相模块

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 7.1 Build 156 04/30/2007 SJ Full Version"

// DATE "08/21/2007 22:08:49"

// 
// Device: Altera EP1C3T144C8 Package TQFP144
// 

// 
// This Verilog file should be used for PrimeTime (Verilog) only
// 

`timescale 1 ps/ 1 ps

module TopLayer (
	Reset,
	MeasureStart,
	SysClock,
	WaveInOne,
	WaveInTwo,
	Select,
	Increase,
	Decrease,
	Double,
	Halve,
	ReadClock,
	DataOut,
	ReadyFlag,
	LeadFlag,
	ClockOut,
	WaveOutOne,
	WaveOutTwo,
	U4Dir,
	U5Dir,
	U6Dir,
	U7Dir,
	U9Dir,
	U10Dir,
	U11Dir,
	LED0,
	LED1,
	LED2,
	LED3);
input 	Reset;
input 	MeasureStart;
input 	SysClock;
input 	WaveInOne;
input 	WaveInTwo;
input 	Select;
input 	Increase;
input 	Decrease;
input 	Double;
input 	Halve;
input 	ReadClock;
output 	DataOut;
output 	ReadyFlag;
output 	LeadFlag;
output 	ClockOut;
output 	[11:0] WaveOutOne;
output 	[11:0] WaveOutTwo;
output 	U4Dir;
output 	U5Dir;
output 	U6Dir;
output 	U7Dir;
output 	U9Dir;
output 	U10Dir;
output 	U11Dir;
output 	LED0;
output 	LED1;
output 	LED2;
output 	LED3;

wire gnd = 1'b0;
wire vcc = 1'b1;

// synopsys translate_off
initial $sdf_annotate("WorkOneBeta_v.sdo");
// synopsys translate_on

wire \ReadU0|SourceData[67]~regout ;
wire \ReadU0|SourceData[74]~regout ;
wire \ReadU0|SourceData[69]~regout ;
wire \ReadU0|SourceData[76]~regout ;
wire \ReadU0|SourceData[71]~regout ;
wire \ReadU0|SourceData[78]~regout ;
wire \ReadU0|SourceData[65]~regout ;
wire \ReadU0|SourceData[72]~regout ;
wire \ReadU0|SourceData[92]~regout ;
wire \ReadU0|SourceData[90]~regout ;
wire \ReadU0|SourceData[85]~regout ;
wire \ReadU0|SourceData[83]~regout ;
wire \ReadU0|SourceData[93]~regout ;
wire \ReadU0|SourceData[91]~regout ;
wire \ReadU0|SourceData[84]~regout ;
wire \ReadU0|SourceData[82]~regout ;
wire \ReadU0|SourceData[51]~regout ;
wire \ReadU0|SourceData[99]~regout ;
wire \ReadU0|SourceData[105]~regout ;
wire \ReadU0|SourceData[57]~regout ;
wire \ReadU0|SourceData[107]~regout ;
wire \ReadU0|SourceData[59]~regout ;
wire \ReadU0|SourceData[49]~regout ;
wire \ReadU0|SourceData[97]~regout ;
wire \ReadU0|SourceData[108]~regout ;
wire \ReadU0|SourceData[60]~regout ;
wire \ReadU0|SourceData[54]~regout ;
wire \ReadU0|SourceData[102]~regout ;
wire \ReadU0|SourceData[110]~regout ;
wire \ReadU0|SourceData[62]~regout ;
wire \ReadU0|SourceData[52]~regout ;
wire \ReadU0|SourceData[100]~regout ;
wire \ReadU0|SourceData[109]~regout ;
wire \ReadU0|SourceData[61]~regout ;
wire \ReadU0|SourceData[55]~regout ;
wire \ReadU0|SourceData[103]~regout ;
wire \ReadU0|SourceData[111]~regout ;
wire \ReadU0|SourceData[63]~regout ;
wire \ReadU0|SourceData[53]~regout ;
wire \ReadU0|SourceData[101]~regout ;
wire \ReadU0|SourceData[50]~regout ;
wire \ReadU0|SourceData[56]~regout ;
wire \ReadU0|SourceData[104]~regout ;
wire \ReadU0|SourceData[98]~regout ;
wire \ReadU0|SourceData[120]~regout ;
wire \ReadU0|SourceData[114]~regout ;
wire \ReadU0|SourceData[34]~regout ;
wire \ReadU0|SourceData[40]~regout ;
wire \MeasureU0|And~combout ;
wire \ReadClock~combout ;
wire \Reset~combout ;
wire \ReadU0|Counter[0]~regout ;
wire \ReadU0|Counter[1]~regout ;
wire \ReadU0|Counter[1]~28 ;
wire \ReadU0|Counter[1]~28COUT1 ;
wire \ReadU0|Counter[2]~regout ;
wire \ReadU0|Counter[2]~27 ;
wire \ReadU0|Counter[2]~27COUT1 ;
wire \ReadU0|Counter[3]~regout ;
wire \ReadU0|Counter[3]~26 ;
wire \ReadU0|Counter[3]~26COUT1 ;
wire \ReadU0|Counter[4]~regout ;
wire \ReadU0|Counter[4]~29 ;
wire \ReadU0|Counter[5]~regout ;
wire \MeasureStart~combout ;
wire \MeasureU0|rFreClockCounter[31]~0_combout ;
wire \MeasureU0|rIndicatorLight~57_combout ;
wire \MeasureU0|rStartExsitFlag~regout ;
wire \MeasureU0|SystemClockDivider|Count[0]~regout ;
wire \MeasureU0|SystemClockDivider|Count[0]~323 ;
wire \MeasureU0|SystemClockDivider|Count[0]~323COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[1]~regout ;
wire \MeasureU0|SystemClockDivider|Count[1]~324 ;
wire \MeasureU0|SystemClockDivider|Count[1]~324COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[2]~regout ;
wire \MeasureU0|SystemClockDivider|Count[2]~325 ;
wire \MeasureU0|SystemClockDivider|Count[2]~325COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[3]~regout ;
wire \MeasureU0|SystemClockDivider|Count[3]~326 ;
wire \MeasureU0|SystemClockDivider|Count[4]~regout ;
wire \MeasureU0|SystemClockDivider|Count[4]~327 ;
wire \MeasureU0|SystemClockDivider|Count[4]~327COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[5]~regout ;
wire \MeasureU0|SystemClockDivider|Count[5]~328 ;
wire \MeasureU0|SystemClockDivider|Count[5]~328COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[6]~regout ;
wire \MeasureU0|SystemClockDivider|Count[6]~329 ;
wire \MeasureU0|SystemClockDivider|Count[6]~329COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[7]~regout ;
wire \MeasureU0|SystemClockDivider|Count[7]~330 ;
wire \MeasureU0|SystemClockDivider|Count[7]~330COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[8]~regout ;
wire \MeasureU0|SystemClockDivider|Count[8]~331 ;
wire \MeasureU0|SystemClockDivider|Count[9]~regout ;
wire \MeasureU0|SystemClockDivider|Count[9]~332 ;
wire \MeasureU0|SystemClockDivider|Count[9]~332COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[10]~regout ;
wire \MeasureU0|SystemClockDivider|Count[10]~333 ;
wire \MeasureU0|SystemClockDivider|Count[10]~333COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[11]~regout ;
wire \MeasureU0|SystemClockDivider|Count[11]~334 ;
wire \MeasureU0|SystemClockDivider|Count[11]~334COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[12]~regout ;
wire \MeasureU0|SystemClockDivider|Count[12]~335 ;
wire \MeasureU0|SystemClockDivider|Count[12]~335COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[13]~regout ;
wire \MeasureU0|SystemClockDivider|Count[13]~336 ;
wire \MeasureU0|SystemClockDivider|Count[14]~regout ;
wire \MeasureU0|SystemClockDivider|Count[14]~337 ;
wire \MeasureU0|SystemClockDivider|Count[14]~337COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[15]~regout ;
wire \MeasureU0|SystemClockDivider|Count[15]~338 ;
wire \MeasureU0|SystemClockDivider|Count[15]~338COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[16]~regout ;
wire \MeasureU0|SystemClockDivider|Count[16]~321 ;
wire \MeasureU0|SystemClockDivider|Count[16]~321COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[17]~regout ;
wire \MeasureU0|SystemClockDivider|Count[17]~320 ;
wire \MeasureU0|SystemClockDivider|Count[17]~320COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[18]~regout ;
wire \MeasureU0|SystemClockDivider|Count[18]~322 ;
wire \MeasureU0|SystemClockDivider|Count[19]~regout ;
wire \MeasureU0|SystemClockDivider|Count[19]~318 ;
wire \MeasureU0|SystemClockDivider|Count[19]~318COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[20]~regout ;
wire \MeasureU0|SystemClockDivider|Count[20]~319 ;
wire \MeasureU0|SystemClockDivider|Count[20]~319COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[21]~regout ;
wire \MeasureU0|SystemClockDivider|Count[21]~339 ;
wire \MeasureU0|SystemClockDivider|Count[21]~339COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[22]~regout ;
wire \MeasureU0|SystemClockDivider|Count[22]~340 ;
wire \MeasureU0|SystemClockDivider|Count[22]~340COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[23]~regout ;
wire \MeasureU0|SystemClockDivider|Count[23]~341 ;
wire \MeasureU0|SystemClockDivider|Count[24]~regout ;
wire \MeasureU0|SystemClockDivider|Count[24]~314 ;
wire \MeasureU0|SystemClockDivider|Count[24]~314COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[25]~regout ;
wire \MeasureU0|SystemClockDivider|Count[25]~315 ;
wire \MeasureU0|SystemClockDivider|Count[25]~315COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[26]~regout ;
wire \MeasureU0|SystemClockDivider|Count[26]~316 ;
wire \MeasureU0|SystemClockDivider|Count[26]~316COUT1 ;
wire \MeasureU0|SystemClockDivider|Count[27]~regout ;
wire \MeasureU0|SystemClockDivider|LessThan0~444_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~452_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~445_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~446_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~447_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~448_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~449_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~450_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~451_combout ;
wire \MeasureU0|SystemClockDivider|LessThan0~453_combout ;
wire \MeasureU0|SystemClockDivider|rVirtualClock~regout ;
wire \MeasureU0|rFreClockCounter[0]~regout ;
wire \MeasureU0|rFreClockCounter[1]~regout ;
wire \MeasureU0|rFreClockCounter[1]~1206 ;
wire \MeasureU0|rFreClockCounter[1]~1206COUT1 ;
wire \MeasureU0|rFreClockCounter[2]~regout ;
wire \MeasureU0|rFreClockCounter[2]~1207 ;
wire \MeasureU0|rFreClockCounter[2]~1207COUT1 ;
wire \MeasureU0|rFreClockCounter[3]~regout ;
wire \MeasureU0|rFreClockCounter[3]~1208 ;
wire \MeasureU0|rFreClockCounter[3]~1208COUT1 ;
wire \MeasureU0|rFreClockCounter[4]~regout ;
wire \MeasureU0|rFreClockCounter[4]~1209 ;
wire \MeasureU0|rFreClockCounter[4]~1209COUT1 ;
wire \MeasureU0|rFreClockCounter[5]~regout ;
wire \MeasureU0|rFreClockCounter[5]~1210 ;
wire \MeasureU0|rFreClockCounter[6]~regout ;
wire \MeasureU0|rFreClockCounter[6]~1211 ;
wire \MeasureU0|rFreClockCounter[6]~1211COUT1 ;
wire \MeasureU0|rFreClockCounter[7]~regout ;
wire \MeasureU0|rFreClockCounter[7]~1212 ;
wire \MeasureU0|rFreClockCounter[7]~1212COUT1 ;
wire \MeasureU0|rFreClockCounter[8]~regout ;
wire \MeasureU0|rFreClockCounter[8]~1213 ;
wire \MeasureU0|rFreClockCounter[8]~1213COUT1 ;
wire \MeasureU0|rFreClockCounter[9]~regout ;
wire \MeasureU0|rFreClockCounter[9]~1214 ;
wire \MeasureU0|rFreClockCounter[9]~1214COUT1 ;
wire \MeasureU0|rFreClockCounter[10]~regout ;
wire \MeasureU0|rFreClockCounter[10]~1215 ;
wire \MeasureU0|rFreClockCounter[11]~regout ;
wire \MeasureU0|rFreClockCounter[11]~1216 ;
wire \MeasureU0|rFreClockCounter[11]~1216COUT1 ;
wire \MeasureU0|rFreClockCounter[12]~regout ;
wire \MeasureU0|rFreClockCounter[12]~1217 ;
wire \MeasureU0|rFreClockCounter[12]~1217COUT1 ;
wire \MeasureU0|rFreClockCounter[13]~regout ;
wire \MeasureU0|rFreClockCounter[13]~1218 ;
wire \MeasureU0|rFreClockCounter[13]~1218COUT1 ;
wire \MeasureU0|rFreClockCounter[14]~regout ;