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📁 Verilog实现的DDS正弦信号发生器和测频测相模块
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    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[2\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (546:546:546) (546:546:546))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[2\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1366:1366:1366) (1366:1366:1366))
        (PORT clk (1315:1315:1315) (1315:1315:1315))
        (PORT ena (1345:1345:1345) (1345:1345:1345))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[3\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (549:549:549) (549:549:549))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[3\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1366:1366:1366) (1366:1366:1366))
        (PORT clk (1315:1315:1315) (1315:1315:1315))
        (PORT ena (1345:1345:1345) (1345:1345:1345))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[4\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (513:513:513) (513:513:513))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[4\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1366:1366:1366) (1366:1366:1366))
        (PORT clk (1315:1315:1315) (1315:1315:1315))
        (PORT ena (1345:1345:1345) (1345:1345:1345))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[5\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (551:551:551) (551:551:551))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout (838:838:838) (838:838:838))
        (IOPATH cin0 cout (271:271:271) (271:271:271))
        (IOPATH cin1 cout (258:258:258) (258:258:258))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[5\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1366:1366:1366) (1366:1366:1366))
        (PORT clk (1315:1315:1315) (1315:1315:1315))
        (PORT ena (1345:1345:1345) (1345:1345:1345))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[6\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (510:510:510) (510:510:510))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[6\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2233:2233:2233) (2233:2233:2233))
        (PORT clk (1316:1316:1316) (1316:1316:1316))
        (PORT ena (2162:2162:2162) (2162:2162:2162))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[7\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (529:529:529) (529:529:529))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[7\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2233:2233:2233) (2233:2233:2233))
        (PORT clk (1316:1316:1316) (1316:1316:1316))
        (PORT ena (2162:2162:2162) (2162:2162:2162))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[8\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (533:533:533) (533:533:533))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[8\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2233:2233:2233) (2233:2233:2233))
        (PORT clk (1316:1316:1316) (1316:1316:1316))
        (PORT ena (2162:2162:2162) (2162:2162:2162))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[9\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (513:513:513) (513:513:513))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[9\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2233:2233:2233) (2233:2233:2233))
        (PORT clk (1316:1316:1316) (1316:1316:1316))
        (PORT ena (2162:2162:2162) (2162:2162:2162))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[10\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (512:512:512) (512:512:512))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin cout (136:136:136) (136:136:136))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[10\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2233:2233:2233) (2233:2233:2233))
        (PORT clk (1316:1316:1316) (1316:1316:1316))
        (PORT ena (2162:2162:2162) (2162:2162:2162))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[11\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (510:510:510) (510:510:510))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[11\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2233:2233:2233) (2233:2233:2233))
        (PORT clk (1316:1316:1316) (1316:1316:1316))
        (PORT ena (2162:2162:2162) (2162:2162:2162))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD ena (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[12\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (529:529:529) (529:529:529))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[12\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (2233:2233:2233) (2233:2233:2233))
        (PORT clk (1316:1316:1316) (1316:1316:1316))
        (PORT ena (2162:2162:2162) (2162:2162:2162))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37
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