workonebeta_v.sdo

Verilog实现的DDS正弦信号发生器和测频测相模块

    (DELAY
      (ABSOLUTE
        (PORT sclr (2261:2261:2261) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD sclr (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[25\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (523:523:523) (523:523:523))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[25\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2261:2261:2261) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD sclr (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[26\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (528:528:528) (528:528:528))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[26\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2261:2261:2261) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD sclr (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[27\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (761:761:761) (761:761:761))
        (IOPATH datad regin (309:309:309) (309:309:309))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[27\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2261:2261:2261) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
      (SETUPHOLD sclr (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~444.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1174:1174:1174) (1174:1174:1174))
        (PORT datab (1151:1151:1151) (1151:1151:1151))
        (PORT datac (1191:1191:1191) (1191:1191:1191))
        (PORT datad (1172:1172:1172) (1172:1172:1172))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~452.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (758:758:758) (758:758:758))
        (PORT datad (738:738:738) (738:738:738))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~445.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (546:546:546) (546:546:546))
        (PORT datab (519:519:519) (519:519:519))
        (PORT datac (559:559:559) (559:559:559))
        (PORT datad (535:535:535) (535:535:535))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~446.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (774:774:774) (774:774:774))
        (PORT datac (1183:1183:1183) (1183:1183:1183))
        (PORT datad (1137:1137:1137) (1137:1137:1137))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~447.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (747:747:747) (747:747:747))
        (PORT datab (731:731:731) (731:731:731))
        (PORT datac (709:709:709) (709:709:709))
        (PORT datad (182:182:182) (182:182:182))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~448.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1607:1607:1607) (1607:1607:1607))
        (PORT datab (1566:1566:1566) (1566:1566:1566))
        (PORT datac (1306:1306:1306) (1306:1306:1306))
        (PORT datad (431:431:431) (431:431:431))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~449.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1292:1292:1292) (1292:1292:1292))
        (PORT datab (1566:1566:1566) (1566:1566:1566))
        (PORT datac (1311:1311:1311) (1311:1311:1311))
        (PORT datad (423:423:423) (423:423:423))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~450.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1592:1592:1592) (1592:1592:1592))
        (PORT datab (1568:1568:1568) (1568:1568:1568))
        (PORT datac (1280:1280:1280) (1280:1280:1280))
        (PORT datad (420:420:420) (420:420:420))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~451.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1281:1281:1281) (1281:1281:1281))
        (PORT datab (1260:1260:1260) (1260:1260:1260))
        (PORT datac (1586:1586:1586) (1586:1586:1586))
        (PORT datad (430:430:430) (430:430:430))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~453.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1203:1203:1203) (1203:1203:1203))
        (PORT datab (666:666:666) (666:666:666))
        (PORT datac (551:551:551) (551:551:551))
        (PORT datad (1230:1230:1230) (1230:1230:1230))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|rVirtualClock.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1663:1663:1663) (1663:1663:1663))
        (PORT datad (557:557:557) (557:557:557))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE MeasureU0\|SystemClockDivider\|rVirtualClock.regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (2141:2141:2141) (2141:2141:2141))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|rVirtualClock.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1261:1261:1261))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1078:1078:1078) (1078:1078:1078))
        (PORT datab (755:755:755) (755:755:755))
        (PORT datac (2123:2123:2123) (2123:2123:2123))
        (PORT datad (1828:1828:1828) (1828:1828:1828))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE MeasureU0\|rFreClockCounter\[0\].regin_datac)
    (DELAY
      (ABSOLUTE
        (PORT IN2 (2601:2601:2601) (2601:2601:2601))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[0\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1366:1366:1366) (1366:1366:1366))
        (PORT clk (1315:1315:1315) (1315:1315:1315))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUPHOLD datain (posedge clk) (37:37:37) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[1\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (546:546:546) (546:546:546))
        (PORT datab (514:514:514) (514:514:514))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|rFreClockCounter\[1\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (1366:1366:1366) (1366:1366:1366))
        (PORT clk (1315:1315:1315) (1315:1315:1315))
        (PORT ena (1345:1345:1345) (1345:1345:1345))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )