adapter.v

Verilog实现的DDS正弦信号发生器和测频测相模块

module Adapter
(
Clock,
FrequencySet,
PhaseSet,
FrequencyKey,
PhaseKey
);
input Clock;
input [9:0] FrequencySet;
input [8:0] PhaseSet;
output [21:0] FrequencyKey;
output [9:0] PhaseKey;

//wire Clock;
//wire [14:0] FrequencySet;
//wire [8:0] PhaseSet;
//wire [23:0] FrequencyKey;
//wire [9:0] PhaseKey;

FreFindTable FreFindTableU0(.address(FrequencySet), .clock(Clock), .q(FrequencyKey));
PhaseFindTable PhaseFindTableU0(.address(PhaseSet), .clock(Clock), .q(PhaseKey));

endmodule