workonebeta.sim.rpt

Verilog实现的DDS正弦信号发生器和测频测相模块

The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------+
; Complete 1/0-Value Coverage                     ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                                                                                                       ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                               ; Output Port Name                                                                                                                  ; Output Port Type ;
+-----------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------+------------------+
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[0]             ; portadataout0    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[1]             ; portadataout1    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[2]             ; portadataout2    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[3]             ; portadataout3    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[4]             ; portadataout0    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[5]             ; portadataout1    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[6]             ; portadataout2    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[7]             ; portadataout3    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[8]             ; portadataout0    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[9]             ; portadataout1    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[10]            ; portadataout2    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU0|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[11]            ; portadataout3    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[0]             ; portadataout0    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[1]             ; portadataout1    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[2]             ; portadataout2    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a0             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[3]             ; portadataout3    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[4]             ; portadataout0    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[5]             ; portadataout1    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[6]             ; portadataout2    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a4             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[7]             ; portadataout3    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[8]             ; portadataout0    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[9]             ; portadataout1    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[10]            ; portadataout2    ;
; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|ram_block1a8             ; |TopLayer|DDS:DDSU0|SinFindTable:SinFindTableU1|altsyncram:altsyncram_component|altsyncram_v531:auto_generated|q_a[11]            ; portadataout3    ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[20]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[20]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[20]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[20]~120                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[20]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[20]~120COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[21]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[21]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[21]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[21]~121                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[21]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[21]~121COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[22]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[22]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[22]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[22]~122                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[22]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[22]~122COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[23]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[23]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[23]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[23]~123                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[23]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[23]~123COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[24]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[24]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[24]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[24]~124                                                                        ; cout             ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[25]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[25]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[25]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[25]~125                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[25]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[25]~125COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[26]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[26]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[26]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[26]~126                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[26]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[26]~126COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[27]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[27]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[27]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[27]~127                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[27]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[27]~127COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[28]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[28]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[28]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[28]~128                                                                        ; cout0            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[28]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[28]~128COUT1                                                                   ; cout1            ;
; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[29]                                                                                  ; |TopLayer|DDS:DDSU0|Accumulater:AccumulaterU0|Base[29]                                                                            ; regout           ;
; |TopLayer|DDS:DDSU0|Add0~147                                                                                                            ; |TopLayer|DDS:DDSU0|Add0~147                                                                                                      ; combout          ;