dds.v

Verilog实现的DDS正弦信号发生器和测频测相模块

module DDS
(
Clock,
FrequencyKey,
PhaseKey,
ClockOut,
WaveOutOne,
WaveOutTwo
);
input Clock;
input [21:0] FrequencyKey;
input [9:0] PhaseKey;
output ClockOut;
output [11:0] WaveOutOne;
output [11:0] WaveOutTwo;

//wire Clock;
//wire [23:0] FrequencyKey;
//wire [9:0] PhaseKey;
//wire ClockOut;
//wire [11:0] WaveOutOne;
//wire [11:0] WaveOutTwo;

assign ClockOut = Clock;

wire [29:0] Acc;
Accumulater AccumulaterU0(.Clock(Clock), .Base(Acc), .Increment(FrequencyKey));

wire [9:0] RomAddress;
assign RomAddress = Acc[29:20];
SinFindTable SinFindTableU0(.address(RomAddress), .clock(Clock), .q(WaveOutOne));
SinFindTable SinFindTableU1(.address(RomAddress + PhaseKey), .clock(Clock), .q(WaveOutTwo));

endmodule