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Verilog实现的DDS正弦信号发生器和测频测相模块

wire \AdjustU0|ScanClockDivider|Count[7]~244COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[8]~245 ;
wire \AdjustU0|ScanClockDivider|Count[9]~246 ;
wire \AdjustU0|ScanClockDivider|Count[9]~246COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[10]~247 ;
wire \AdjustU0|ScanClockDivider|Count[10]~247COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[11]~248 ;
wire \AdjustU0|ScanClockDivider|Count[11]~248COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[12]~249 ;
wire \AdjustU0|ScanClockDivider|Count[12]~249COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[13]~250 ;
wire \AdjustU0|ScanClockDivider|Count[14]~251 ;
wire \AdjustU0|ScanClockDivider|Count[14]~251COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[15]~252 ;
wire \AdjustU0|ScanClockDivider|Count[15]~252COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[16]~253 ;
wire \AdjustU0|ScanClockDivider|Count[16]~253COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[17]~254 ;
wire \AdjustU0|ScanClockDivider|Count[17]~254COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[18]~255 ;
wire \AdjustU0|ScanClockDivider|Count[19]~256 ;
wire \AdjustU0|ScanClockDivider|Count[19]~256COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[20]~257 ;
wire \AdjustU0|ScanClockDivider|Count[20]~257COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[21]~258 ;
wire \AdjustU0|ScanClockDivider|Count[21]~258COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[22]~259 ;
wire \AdjustU0|ScanClockDivider|Count[22]~259COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[23]~260 ;
wire \AdjustU0|ScanClockDivider|Count[24]~261 ;
wire \AdjustU0|ScanClockDivider|Count[24]~261COUT1 ;
wire \AdjustU0|ScanClockDivider|Count[25]~262 ;
wire \AdjustU0|ScanClockDivider|Count[25]~262COUT1 ;
wire \AdjustU0|ScanClockDivider|LessThan0~463_combout ;
wire \AdjustU0|ScanClockDivider|LessThan0~462_combout ;
wire \AdjustU0|ScanClockDivider|LessThan0~460_combout ;
wire \AdjustU0|ScanClockDivider|LessThan0~458_combout ;
wire \AdjustU0|ScanClockDivider|LessThan0~457_combout ;
wire \AdjustU0|ScanClockDivider|LessThan0~459_combout ;
wire \AdjustU0|ScanClockDivider|LessThan0~461_combout ;
wire \AdjustU0|ScanClockDivider|Count[26]~263 ;
wire \AdjustU0|ScanClockDivider|Count[26]~263COUT1 ;
wire \AdjustU0|ScanClockDivider|LessThan0~464_combout ;
wire \AdjustU0|ScanClockDivider|rVirtualClock~regout ;
wire \AdjustU0|rIndicatorLight~13_combout ;
wire \Select~_wirecell_combout ;
wire \AdjustU0|rIndicatorLight~regout ;
wire \MeasureU0|rIndicatorLightB~regout ;
wire [6:0] \ReadU0|Counter ;
wire [127:0] \ReadU0|SourceData ;
wire [31:0] \MeasureU0|rFreClockCounter ;
wire [31:0] \MeasureU0|rFreWaveCounter ;
wire [31:0] \MeasureU0|rPhaseWaveCounter ;
wire [11:0] \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a ;
wire [29:0] \DDSU0|AccumulaterU0|Base ;
wire [9:0] \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a ;
wire [21:0] \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a ;
wire [27:0] \AdjustU0|ScanClockDivider|Count ;
wire [9:0] \AdjustU0|rSetFrequency ;
wire [8:0] \AdjustU0|rSetPhase ;
wire [27:0] \MeasureU0|SystemClockDivider|Count ;
wire [11:0] \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a ;

wire [3:0] \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [3:0] \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
wire [3:0] \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
wire [3:0] \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [3:0] \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus ;
wire [3:0] \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus ;
wire [3:0] \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus ;
wire [8:0] \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
wire [0:0] \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
wire [3:0] \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus ;
wire [3:0] \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus ;
wire [3:0] \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
wire [3:0] \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus ;
wire [1:0] \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus ;

assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [0] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [1] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [2] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [3] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];

assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [4] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [5] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [1];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [6] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [2];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [7] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [3];

assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [8] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [9] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [1];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [10] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [2];
assign \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|q_a [11] = \DDSU0|SinFindTableU0|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [3];

assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [0] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [1] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [2] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [3] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];

assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [4] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [0];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [5] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [1];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [6] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [2];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [7] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a4_PORTADATAOUT_bus [3];

assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [8] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [0];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [9] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [1];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [10] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [2];
assign \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|q_a [11] = \DDSU0|SinFindTableU1|altsyncram_component|auto_generated|ram_block1a8_PORTADATAOUT_bus [3];

assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [20] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [0];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [21] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [1];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [19] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [2];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [18] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a20_PORTADATAOUT_bus [3];

assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [0] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [1] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [2] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [3] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [4] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [5] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [6] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [7] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];
assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [8] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [8];

assign \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|q_a [9] = \AdapterU0|PhaseFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];

assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [17] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [0];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [16] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [1];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [15] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [2];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [14] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a17_PORTADATAOUT_bus [3];

assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [13] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [0];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [12] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [1];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [11] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [2];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [10] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a13_PORTADATAOUT_bus [3];

assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [9] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [8] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [1];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [7] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [2];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [6] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a9_PORTADATAOUT_bus [3];

assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [5] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [0];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [4] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [1];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [3] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [2];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [2] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a5_PORTADATAOUT_bus [3];

assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [1] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [0];
assign \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|q_a [0] = \AdapterU0|FreFindTableU0|altsyncram_component|auto_generated|ram_block1a1_PORTADATAOUT_bus [1];

// atom is at LC_X24_Y6_N2
cyclone_lcell \MeasureU0|And (
// Equation(s):
// \MeasureU0|And~combout  = LCELL(\SysClock~combout  & (\WaveInOne~combout  $ \WaveInTwo~combout ))

	.clk(gnd),
	.dataa(vcc),
	.datab(\SysClock~combout ),
	.datac(\WaveInOne~combout ),
	.datad(\WaveInTwo~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\MeasureU0|And~combout ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \MeasureU0|And .lut_mask = "0cc0";
defparam \MeasureU0|And .operation_mode = "normal";
defparam \MeasureU0|And .output_mode = "comb_only";
defparam \MeasureU0|And .register_cascade_mode = "off";
defparam \MeasureU0|And .sum_lutc_input = "datac";
defparam \MeasureU0|And .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_10
cyclone_io \ReadClock~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\ReadClock~combout ),
	.regout(),
	.padio(ReadClock));
// synopsys translate_off
defparam \ReadClock~I .input_async_reset = "none";
defparam \ReadClock~I .input_power_up = "low";
defparam \ReadClock~I .input_register_mode = "none";
defparam \ReadClock~I .input_sync_reset = "none";
defparam \ReadClock~I .oe_async_reset = "none";
defparam \ReadClock~I .oe_power_up = "low";
defparam \ReadClock~I .oe_register_mode = "none";
defparam \ReadClock~I .oe_sync_reset = "none";
defparam \ReadClock~I .operation_mode = "input";
defparam \ReadClock~I .output_async_reset = "none";
defparam \ReadClock~I .output_power_up = "low";
defparam \ReadClock~I .output_register_mode = "none";
defparam \ReadClock~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at PIN_134
cyclone_io \Reset~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\Reset~combout ),
	.regout(),
	.padio(Reset));
// synopsys translate_off
defparam \Reset~I .input_async_reset = "none";
defparam \Reset~I .input_power_up = "low";
defparam \Reset~I .input_register_mode = "none";
defparam \Reset~I .input_sync_reset = "none";
defparam \Reset~I .oe_async_reset = "none";
defparam \Reset~I .oe_power_up = "low";
defparam \Reset~I .oe_register_mode = "none";
defparam \Reset~I .oe_sync_reset = "none";
defparam \Reset~I .operation_mode = "input";
defparam \Reset~I .output_async_reset = "none";
defparam \Reset~I .output_power_up = "low";
defparam \Reset~I .output_register_mode = "none";
defparam \Reset~I .output_sync_reset = "none";
// synopsys translate_on

// atom is at LC_X12_Y6_N6
cyclone_lcell \ReadU0|Counter[0] (
// Equation(s):
// \ReadU0|Counter [0] = DFFEAS(!\ReadU0|Counter [0], GLOBAL(\ReadClock~combout ), !GLOBAL(\Reset~combout ), , , , , , )

	.clk(\ReadClock~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\ReadU0|Counter [0]),
	.aclr(\Reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\ReadU0|Counter [0]),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \ReadU0|Counter[0] .lut_mask = "00ff";
defparam \ReadU0|Counter[0] .operation_mode = "normal";
defparam \ReadU0|Counter[0] .output_mode = "reg_only";
defparam \ReadU0|Counter[0] .register_cascade_mode = "off";
defparam \ReadU0|Counter[0] .sum_lutc_input = "datac";
defparam \ReadU0|Counter[0] .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X16_Y3_N1
cyclone_lcell \ReadU0|Counter[1] (
// Equation(s):
// \ReadU0|Counter [1] = DFFEAS(\ReadU0|Counter [0] $ \ReadU0|Counter [1], GLOBAL(\ReadClock~combout ), !GLOBAL(\Reset~combout ), , , , , , )
// \ReadU0|Counter[1]~28  = CARRY(\ReadU0|Counter [0] & \ReadU0|Counter [1])
// \ReadU0|Counter[1]~28COUT1  = CARRY(\ReadU0|Counter [0] & \ReadU0|Counter [1])

	.clk(\ReadClock~combout ),
	.dataa(\ReadU0|Counter [0]),
	.datab(\ReadU0|Counter [1]),
	.datac(vcc),
	.datad(vcc),
	.aclr(\Reset~combout ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),