workonebeta_v.sdo

Verilog实现的DDS正弦信号发生器和测频测相模块

  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[23\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (502:502:502) (512:512:512))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin cout (136:136:136) (136:136:136))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[23\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2161:2161:2161) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[24\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (499:499:499) (510:510:510))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[24\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2161:2161:2161) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[25\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (506:506:506) (523:523:523))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[25\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2161:2161:2161) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[26\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (512:512:512) (528:528:528))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[26\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2161:2161:2161) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[27\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (761:761:761) (759:759:759))
        (IOPATH datad regin (309:309:309) (309:309:309))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[27\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2161:2161:2161) (2261:2261:2261))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~444.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1121:1121:1121) (1174:1174:1174))
        (PORT datab (1098:1098:1098) (1151:1151:1151))
        (PORT datac (1121:1121:1121) (1191:1191:1191))
        (PORT datad (1126:1126:1126) (1172:1172:1172))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~452.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (723:723:723) (758:758:758))
        (PORT datad (728:728:728) (738:738:738))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~445.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (539:539:539) (546:546:546))
        (PORT datab (509:509:509) (519:519:519))
        (PORT datac (532:532:532) (559:559:559))
        (PORT datad (531:531:531) (535:535:535))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~446.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (762:762:762) (774:774:774))
        (PORT datac (1113:1113:1113) (1183:1183:1183))
        (PORT datad (1089:1089:1089) (1137:1137:1137))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~447.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (729:729:729) (747:747:747))
        (PORT datab (716:716:716) (731:731:731))
        (PORT datac (679:679:679) (709:709:709))
        (PORT datad (182:182:182) (182:182:182))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~448.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1551:1551:1551) (1607:1607:1607))
        (PORT datab (1508:1508:1508) (1566:1566:1566))
        (PORT datac (1241:1241:1241) (1306:1306:1306))
        (PORT datad (425:425:425) (431:431:431))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~449.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1247:1247:1247) (1292:1292:1292))
        (PORT datab (1518:1518:1518) (1566:1566:1566))
        (PORT datac (1256:1256:1256) (1311:1311:1311))
        (PORT datad (414:414:414) (423:423:423))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~450.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1536:1536:1536) (1592:1592:1592))
        (PORT datab (1521:1521:1521) (1568:1568:1568))
        (PORT datac (1215:1215:1215) (1280:1280:1280))
        (PORT datad (412:412:412) (420:420:420))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~451.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1239:1239:1239) (1281:1281:1281))
        (PORT datab (1212:1212:1212) (1260:1260:1260))
        (PORT datac (1525:1525:1525) (1586:1586:1586))
        (PORT datad (424:424:424) (430:430:430))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|LessThan0\~453.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1151:1151:1151) (1203:1203:1203))
        (PORT datab (649:649:649) (666:666:666))
        (PORT datac (522:522:522) (551:551:551))
        (PORT datad (1200:1200:1200) (1230:1230:1230))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|rVirtualClock.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (1628:1628:1628) (1663:1663:1663))
        (PORT datad (557:557:557) (549:549:549))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|rVirtualClock.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|rFreClockCounter\[0\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (1062:1062:1062) (1078:1078:1078))
        (PORT datab (752:752:752) (755:755:755))
        (PORT datac (2101:2101:2101) (2123:2123:2123))
        (PORT datad (1828:1828:1828) (1812:1812:1812))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))