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📁 Verilog实现的DDS正弦信号发生器和测频测相模块
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  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[2\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (509:509:509) (519:519:519))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[2\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[3\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (510:510:510) (519:519:519))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[3\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[4\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (499:499:499) (510:510:510))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[4\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[5\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (521:521:521) (533:533:533))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[5\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[6\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (530:530:530) (540:540:540))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[6\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[7\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (499:499:499) (512:512:512))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[7\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[8\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (530:530:530) (541:541:541))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout (838:838:838) (838:838:838))
        (IOPATH cin cout (208:208:208) (208:208:208))
        (IOPATH cin0 cout (271:271:271) (271:271:271))
        (IOPATH cin1 cout (258:258:258) (258:258:258))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[8\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2310:2310:2310) (2395:2395:2395))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1265:1265:1265) (1245:1245:1245))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[9\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (498:498:498) (510:510:510))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[9\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2336:2336:2336) (2420:2420:2420))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[10\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (515:515:515) (529:529:529))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[10\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2336:2336:2336) (2420:2420:2420))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[11\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (521:521:521) (533:533:533))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[11\].lereg)
    (DELAY
      (ABSOLUTE
        (PORT sclr (2336:2336:2336) (2420:2420:2420))
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1261:1261:1261) (1241:1241:1241))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP sclr (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD sclr (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE MeasureU0\|SystemClockDivider\|Count\[12\].lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (500:500:500) (513:513:513))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
💿 文件大小 1340 K
👤 上传用户 xiaoluya54
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#Verilog #DDS #正弦信号发生器 #模块
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