📄 shift_16.rpt
字号:
27 -> * | - - - - * - - - | <-- d7
12 -> * | - - - - * - - * | <-- stld
LC116-> * | - - - - * - - - | <-- |74165:2|:93
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\maxpluse\my_lib\shift_16\shift_16.rpt
shift_16
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+----------------------------- LC117 Data_out
| +--------------------------- LC126 |74165:1|:37
| | +------------------------- LC125 |74165:1|:38
| | | +----------------------- LC124 |74165:1|:65
| | | | +--------------------- LC122 |74165:1|:70
| | | | | +------------------- LC127 |74165:1|:79
| | | | | | +----------------- LC120 |74165:1|:84
| | | | | | | +--------------- LC119 |74165:1|:93
| | | | | | | | +------------- LC118 |74165:2|:37
| | | | | | | | | +----------- LC123 |74165:2|:38
| | | | | | | | | | +--------- LC121 |74165:2|:65
| | | | | | | | | | | +------- LC113 |74165:2|:70
| | | | | | | | | | | | +----- LC114 |74165:2|:79
| | | | | | | | | | | | | +--- LC115 |74165:2|:84
| | | | | | | | | | | | | | +- LC116 |74165:2|:93
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC126-> - - - * - - - - - - - - - - - | - - - - - - - * | <-- |74165:1|:37
LC125-> - * - - - - - - - - - - - - - | - - - - - - - * | <-- |74165:1|:38
LC124-> - - - - * - - - - - - - - - - | - - - - - - - * | <-- |74165:1|:65
LC122-> - - - - - * - - - - - - - - - | - - - - - - - * | <-- |74165:1|:70
LC127-> - - - - - - * - - - - - - - - | - - - - - - - * | <-- |74165:1|:79
LC120-> - - - - - - - * - - - - - - - | - - - - - - - * | <-- |74165:1|:84
LC119-> * - - - - - - - - - - - - - - | - - - - - - - * | <-- |74165:1|:93
LC118-> - - - - - - - - - - * - - - - | - - - - - - - * | <-- |74165:2|:37
LC123-> - - - - - - - - * - - - - - - | - - - - - - - * | <-- |74165:2|:38
LC121-> - - - - - - - - - - - * - - - | - - - - - - - * | <-- |74165:2|:65
LC113-> - - - - - - - - - - - - * - - | - - - - - - - * | <-- |74165:2|:70
LC114-> - - - - - - - - - - - - - * - | - - - - - - - * | <-- |74165:2|:79
LC115-> - - - - - - - - - - - - - - * | - - - - - - - * | <-- |74165:2|:84
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
20 -> - - - - - - - - - * - - - - - | - - - - - - - * | <-- d0
17 -> - - - - - - - - * - - - - - - | - - - - - - - * | <-- d1
16 -> - - - - - - - - - - * - - - - | - - - - - - - * | <-- d2
15 -> - - - - - - - - - - - * - - - | - - - - - - - * | <-- d3
31 -> - - - - - - - - - - - - * - - | - - - - - - - * | <-- d4
29 -> - - - - - - - - - - - - - * - | - - - - - - - * | <-- d5
41 -> - - - - - - - - - - - - - - * | - - - - - - - * | <-- d6
21 -> - - * - - - - - - - - - - - - | - - - - - - - * | <-- d8
4 -> - * - - - - - - - - - - - - - | - - - - - - - * | <-- d9
11 -> - - - * - - - - - - - - - - - | - - - - - - - * | <-- d10
10 -> - - - - * - - - - - - - - - - | - - - - - - - * | <-- d11
9 -> - - - - - * - - - - - - - - - | - - - - - - - * | <-- d12
8 -> - - - - - - * - - - - - - - - | - - - - - - - * | <-- d13
6 -> - - - - - - - * - - - - - - - | - - - - - - - * | <-- d14
5 -> * - - - - - - - - - - - - - - | - - - - - - - * | <-- d15
18 -> - - - - - - - - - * - - - - - | - - - - - - - * | <-- SER
12 -> * * * * * * * * * * * * * * * | - - - - * - - * | <-- stld
LC77 -> - - * - - - - - - - - - - - - | - - - - - - - * | <-- |74165:2|QH
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\maxpluse\my_lib\shift_16\shift_16.rpt
shift_16
** EQUATIONS **
clk : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
d8 : INPUT;
d9 : INPUT;
d10 : INPUT;
d11 : INPUT;
d12 : INPUT;
d13 : INPUT;
d14 : INPUT;
d15 : INPUT;
SER : INPUT;
stld : INPUT;
-- Node name is 'Data_out' = '|74165:1|QH'
-- Equation name is 'Data_out', type is output
Data_out = DFFE( _LC119 $ GND, GLOBAL( clk), !_EQ001, !_EQ002, VCC);
_EQ001 = !d15 & !stld;
_EQ002 = d15 & !stld;
-- Node name is '|74165:1|:37'
-- Equation name is '_LC126', type is buried
_LC126 = DFFE( _LC125 $ GND, GLOBAL( clk), !_EQ003, !_EQ004, VCC);
_EQ003 = !d9 & !stld;
_EQ004 = d9 & !stld;
-- Node name is '|74165:1|:38'
-- Equation name is '_LC125', type is buried
_LC125 = DFFE( _LC077 $ GND, GLOBAL( clk), !_EQ005, !_EQ006, VCC);
_EQ005 = !d8 & !stld;
_EQ006 = d8 & !stld;
-- Node name is '|74165:1|:65'
-- Equation name is '_LC124', type is buried
_LC124 = DFFE( _LC126 $ GND, GLOBAL( clk), !_EQ007, !_EQ008, VCC);
_EQ007 = !d10 & !stld;
_EQ008 = d10 & !stld;
-- Node name is '|74165:1|:70'
-- Equation name is '_LC122', type is buried
_LC122 = DFFE( _LC124 $ GND, GLOBAL( clk), !_EQ009, !_EQ010, VCC);
_EQ009 = !d11 & !stld;
_EQ010 = d11 & !stld;
-- Node name is '|74165:1|:79'
-- Equation name is '_LC127', type is buried
_LC127 = DFFE( _LC122 $ GND, GLOBAL( clk), !_EQ011, !_EQ012, VCC);
_EQ011 = !d12 & !stld;
_EQ012 = d12 & !stld;
-- Node name is '|74165:1|:84'
-- Equation name is '_LC120', type is buried
_LC120 = DFFE( _LC127 $ GND, GLOBAL( clk), !_EQ013, !_EQ014, VCC);
_EQ013 = !d13 & !stld;
_EQ014 = d13 & !stld;
-- Node name is '|74165:1|:93'
-- Equation name is '_LC119', type is buried
_LC119 = DFFE( _LC120 $ GND, GLOBAL( clk), !_EQ015, !_EQ016, VCC);
_EQ015 = !d14 & !stld;
_EQ016 = d14 & !stld;
-- Node name is '|74165:2|:98' = '|74165:2|QH'
-- Equation name is '_LC077', type is buried
_LC077 = DFFE( _LC116 $ GND, GLOBAL( clk), !_EQ017, !_EQ018, VCC);
_EQ017 = !d7 & !stld;
_EQ018 = d7 & !stld;
-- Node name is '|74165:2|:37'
-- Equation name is '_LC118', type is buried
_LC118 = DFFE( _LC123 $ GND, GLOBAL( clk), !_EQ019, !_EQ020, VCC);
_EQ019 = !d1 & !stld;
_EQ020 = d1 & !stld;
-- Node name is '|74165:2|:38'
-- Equation name is '_LC123', type is buried
_LC123 = DFFE( SER $ GND, GLOBAL( clk), !_EQ021, !_EQ022, VCC);
_EQ021 = !d0 & !stld;
_EQ022 = d0 & !stld;
-- Node name is '|74165:2|:65'
-- Equation name is '_LC121', type is buried
_LC121 = DFFE( _LC118 $ GND, GLOBAL( clk), !_EQ023, !_EQ024, VCC);
_EQ023 = !d2 & !stld;
_EQ024 = d2 & !stld;
-- Node name is '|74165:2|:70'
-- Equation name is '_LC113', type is buried
_LC113 = DFFE( _LC121 $ GND, GLOBAL( clk), !_EQ025, !_EQ026, VCC);
_EQ025 = !d3 & !stld;
_EQ026 = d3 & !stld;
-- Node name is '|74165:2|:79'
-- Equation name is '_LC114', type is buried
_LC114 = DFFE( _LC113 $ GND, GLOBAL( clk), !_EQ027, !_EQ028, VCC);
_EQ027 = !d4 & !stld;
_EQ028 = d4 & !stld;
-- Node name is '|74165:2|:84'
-- Equation name is '_LC115', type is buried
_LC115 = DFFE( _LC114 $ GND, GLOBAL( clk), !_EQ029, !_EQ030, VCC);
_EQ029 = !d5 & !stld;
_EQ030 = d5 & !stld;
-- Node name is '|74165:2|:93'
-- Equation name is '_LC116', type is buried
_LC116 = DFFE( _LC115 $ GND, GLOBAL( clk), !_EQ031, !_EQ032, VCC);
_EQ031 = !d6 & !stld;
_EQ032 = d6 & !stld;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\maxpluse\my_lib\shift_16\shift_16.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:03
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,889K
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