spi.c

嵌入式系统mcf5272华恒光盘开发板附源代码spi

#define MCF5272_GPIO_PACNT	(0x0080)
#define MCF5272_GPIO_PDCNT	(0x0098)
#define MCF5272_QSPI_QMR	(0x00A0)
#define MCF5272_QSPI_QDLYR	(0x00A4) 
#define MCF5272_QSPI_QIR	(0x00AC)
#define MCF5272_QSPI_QAR	(0x00B0)
#define MCF5272_QSPI_QDR	(0x00B4)
#define MCF5272_QSPI_QWR	(0x00A8)
#define MCF5272_MBAR		0x10000000

main()
{
	
	//enable QSPI_CS1
	*(volatile unsigned int*)(MCF5272_GPIO_PACNT + MCF5272_MBAR) = 0x00800000;
	
	//eight bits
	*(volatile unsigned short*)(MCF5272_QSPI_QMR + MCF5272_MBAR) = 0x8308;	
	
	//QDLYR[SPE]=0 [QCD]=0000010 [DTL]=00000000
	*(volatile unsigned short*)(MCF5272_QSPI_QDLYR + MCF5272_MBAR) = 0x0020;	
	
	//enable write collision,abort bus errors,clear any interupts
	*(volatile unsigned short*)(MCF5272_QSPI_QIR + MCF5272_MBAR) = 0xD00F;	
	
	//select the first command RAM entry
	*(volatile unsigned short*)(MCF5272_QSPI_QAR + MCF5272_MBAR) = 0x0020;

	//select chip 1 for each queue entry
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x7200;	
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x7200;	
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x7200;	
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x7200;	
	

	//select the first transmit RAM entry	
	*(volatile unsigned short*)(MCF5272_QSPI_QAR + MCF5272_MBAR) = 0x0000;	
		
	//data to transmit
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x0048; 
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x00BA;
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x007A;
	*(volatile unsigned short*)(MCF5272_QSPI_QDR + MCF5272_MBAR) = 0x004E;	
	
	//set up a queue beginning at entry 0,ending at entry 3
	*(volatile unsigned short*)(MCF5272_QSPI_QWR + MCF5272_MBAR) = 0x0400;	
	
	//set up QDLYR[SPE] to enable the transfers
	*(volatile unsigned short*)(MCF5272_QSPI_QDLYR + MCF5272_MBAR) = 0x8020;	
				
	printf("ok\n");
	
}