irq.h

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#ifndef _INTERRUPT_H
#define _INTERRUPT_H
#include "../s3c2410/cpu.h"
#define EINT0 		0
#define EINT1 		1
#define EINT2 		2
#define EINT3 		3
#define EINT4_7 	4
#define EINT8_23 	5
#define Reserved_1 	6
#define nBATT_FLT	7
#define INT_TICK 	8
#define INT_WDT		9
#define INT_TIMER0	10
#define INT_TIMER1	11
#define INT_TIMER2	12
#define INT_TIMER3	13
#define INT_TIMER4	14
#define INT_UART2	15
#define INT_LCD		16
#define INT_DMA0	17 
#define INT_DMA1	18 
#define INT_DMA2	19 
#define INT_DMA3	20 
#define INT_SDI		21 
#define INT_SPI0	22 
#define INT_UART1	23 
#define Reserved_2	24 
#define INT_USBD	25 
#define INT_USBH	26 
#define INT_IIC		27 
#define INT_UART0	28 
#define INT_SPI1	29 
#define INT_RTC		30 
#define INT_ADC 	31

#define SUB_INT_RXD0 	0
#define SUB_INT_TXD0 	1
#define SUB_INT_ERR0 	2
#define SUB_INT_RXD1 	3
#define SUB_INT_TXD1 	4
#define SUB_INT_ERR1 	5
#define SUB_INT_RXD2 	6
#define SUB_INT_TXD2 	7
#define SUB_INT_ERR2 	8
#define SUB_INT_TC	9
#define SUB_INT_ADC	10


#define IRQ_MASK	1
#define IRQ_UNMASK	0

#define ARB_SEL0 	0
#define ARB_SEL1 	1
#define ARB_SEL2 	2
#define ARB_SEL3 	3
#define ARB_SEL4 	4
#define ARB_SEL5 	5
#define ARB_SEL6 	6

#define PRIO_ORDER_SET_0 0
#define PRIO_ORDER_SET_1 1
#define PRIO_ORDER_SET_2 2
#define PRIO_ORDER_SET_3 3

#define ARB_MODE0 	0
#define ARB_MODE1 	1
#define ARB_MODE2 	2
#define ARB_MODE3 	3
#define ARB_MODE4 	4
#define ARB_MODE5 	5
#define ARB_MODE6 	6

#define PRIO_ROTATE_ENABLE 1
#define PRIO_ROTATE_DISABLE 0


struct irq_ctrl_object
{
	volatile unsigned int	*src_pnd;
	volatile unsigned int	*sub_src_pnd;
	volatile unsigned int	*int_mod;
	volatile unsigned int	*int_msk;
	volatile unsigned int	*sub_int_msk;
	volatile unsigned int	*priority;
	volatile unsigned int	*int_pnd;
	volatile unsigned int	*int_offset;

};


typedef void(* irq_ptr)(struct cpu_registers *regs);

#endif _INTERRUPT_H