iis.c

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/*
 *	ApOS (Another Project software for s3c2410)
 *	
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License version 2 as
 *	published by the Free Software Foundation.
 *			
 *						Copyright caiyuqing
 *
 */
#include "../include/s3c2410/s3c2410.h"
#include "../include/s3c2410/iis.h"
#include "../include/s3c2410/dma.h"
#include "../include/s3c2410/cpu.h"
#include "../include/kernel/irq.h"

extern char sys_dma2_done;
extern irq_ptr irq_rotunie[32];
extern struct dma_ctrl_object 	dma_ctrl_object;
void iis_dma2_irq(struct cpu_registers *regs);

struct iis_control_obj iis_control_obj;

void iis_ctrl_obj_init(struct iis_control_obj *iisco)
{
	iisco->iiscon	=&rIISCON;
	iisco->iismod	=&rIISMOD;
	iisco->iispsr	=&rIISPSR;
	iisco->iisfcon	=&rIISFCON;
	iisco->iisfifo	=&rIISFIFO;
}

/*
 *	设置sdi的DMA通道
 */
void iis_dma_setup(unsigned int *mem_addr,int len)
{
	struct dma_ctrl_object *dma_obj	=&dma_ctrl_object;
	struct dma_chanel *dma_chanel	=((struct dma_chanel *)dma_obj)+DMA_CHANEL_2;
	unsigned int tc=len;

	irq_rotunie[INT_DMA2]	=&iis_dma2_irq;
	irq_mask(INT_DMA2,IRQ_UNMASK);
	sys_dma2_done=0;//dma标志清0，若sys_dma2_done为1表示dma操作已经完成
	

	*dma_chanel->disrcc=(AHB<<LOC_OFFSET)|(INCREMENT<<INC_OFFSET);
	*dma_chanel->didstc=(APB<<LOC_OFFSET)|(FIXED<<INC_OFFSET);
	*dma_chanel->disrc=mem_addr;
	*dma_chanel->didst=iis_control_obj.iisfifo;
		

	/*
	 *	sdi的DMA通道的属性设置
	 *	具体信息可查看dma.c 398行~434行
	 */
	*dma_chanel->dcon=(1<<DMD_HS_OFFSET)|(0<<SYNC_OFFSET)|
			(1<<INT_OFFSET)|(0<<TSZ_OFFSET)|(1<<SERVMODE_OFFSET)|(0<<HWSRCSEL_OFFSET)|
			(1<<SWHW_SEL_OFFSET)|(1<<RELOAD_OFFSET)|(BYTE<<DSZ_OFFSET)|(tc);

	/*
	 *	打开sdi的DMA通道
	 */
	*dma_chanel->dmasktrig=(0<<STOP_OFFSET)|(1<<ON_OFF_OFFSET)|0;
}

/*
 *	dma2中断服务例程
 */
void iis_dma2_irq(struct cpu_registers *regs)
{
	clean_src_pnd(INT_DMA2);
	clean_int_pnd(INT_DMA2);
	irq_mask(INT_DMA2,IRQ_MASK);

	dma_stop(DMA_CHANEL_2);
	sys_dma2_done=1;//sys_dma2_done设为1，表示DMA操作完成
}
int fs;

#define BLOCK(n) ((n)*32*512)

void iis_test()
{
	UDA1341TS_init();
	nf_read(BLOCK(60),0x33000000,1024*215);
	iis_dma_setup(0x33000000,1024*215);
	//fs=*((unsigned int *)0x33000000 + 0x1c) | *((unsigned int *)0x33000000 + 0x1d)<<8 | 
	//*((unsigned int *)0x33000000 + 0x1e)<<16 | *((unsigned int *)0x33000000 + 0x1f)<<24;
	
	
	
	if(fs==44100)               //11.2896MHz(256fs)
	{
		*iis_control_obj.iispsr= (2<<5) + 2;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)
	}
	else
	{
		*iis_control_obj.iispsr= (5<<5) + 5;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)
	}
	*iis_control_obj.iiscon = (1<<5) + (1<<2) + (1<<1);         //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
	//Master mode[8],Tx mode[7:6],Low for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
	*iis_control_obj.iismod = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
    
	*iis_control_obj.iisfcon = (1<<15) + (1<<13);        //Tx DMA,Tx FIFO --> start piling....
	//IIS Tx Start
	*iis_control_obj.iiscon|= 0x1;             //IIS Interface start
}