cpu.c

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/*
 *	ApOS (Another Project software for s3c2410)
 *	
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License version 2 as
 *	published by the Free Software Foundation.
 *			
 *						Copyright caiyuqing
 *
 */
#include "../include/s3c2410/s3c2410.h"
#include "../include/s3c2410/cpu.h"
/*
 *	读控制寄存器
 */
unsigned int read_control_register()
{
	unsigned int reg;
	
	asm volatile(
		"mrc p15,0,r0,c1,c0,0 \n\t"
		"str r0,%0 \n\t"
		:
		:"m"(reg)
		:"r0"
	);
	
	reg&=~(0x7FFF)<<15;
	reg&=~(0x3)<<10;
	reg|=0xf<<3;

	return reg;
}
/*
 *	写控制寄存器
 */
void write_control_register(unsigned int value)
{
	asm volatile(
		"ldr r0,%0 \n\t"
		"mcr p15,0,r0,c1,c0,0 \n\t"
		:
		:"m"(value)
		:"r0"
	);
}

void set_ctrl_bit(unsigned int* reg_data,unsigned char offset,unsigned char bit)
{
	*reg_data&=~(0x1)<<offset;
	*reg_data|=bit<<offset;
}
/*
 *	读 cpsr 寄存器
 */
unsigned int read_cpsr()
{
	unsigned int reg;
	
	asm volatile(
		"mrs r1,cpsr \n\t"
		"str r1,%0 \n\t"
		:
		:"m"(reg)
		:"memory","r1"
	);
	return reg;
}

/*
 *	写 cpsr 寄存器
 */
void write_cpsr(unsigned int reg)
{
	asm volatile(
		"ldr r1,%0 \n\t"
		"msr cpsr,r1 \n\t"
		:
		:"m"(reg)
		:"r1"
	);
}

/*
 *	读 spsr 寄存器
 */
unsigned int read_spsr()
{
	unsigned int reg;
	
	asm volatile(
		"mrs r1,spsr \n\t"
		"str r1,%0 \n\t"
		:
		:"m"(reg)
		:"memory","r1"
	);
	return reg;
}
/*
 *	写 spsr 寄存器
 */
unsigned int write_spsr(unsigned int reg)
{
	asm volatile(
		"ldr r1,%0 \n\t"
		"msr spsr,r1 \n\t"
		:
		:"m"(reg)
		:"memory","r1"
	);
}

/*
 *	切换cpu模式
 */
void switch_cpu_mode(unsigned char mode)
{
	unsigned int reg;
	
	reg=read_cpsr();
	reg&=~(0x1f);
	reg|=mode;
	write_cpsr(reg);
}

/*
 *	读data fault status register
 */
unsigned int read_data_fsr()
{
	unsigned int reg;
	asm volatile(
		"mrc p15,0,r0,c5,c0,0 \n\t"
		"str r0,%0 \n\t"
		:
		:"m"(reg)
		:"r0"
	);
	return reg;
}

/*
 *	写data fault status register
 */
void write_data_fsr(unsigned int reg)
{
	asm volatile(
		"ldr r0,%0 \n\t"
		"mcr p15,0,r0,c5,c0,0 \n\t"
		:
		:"mem"(reg)
		:"r0"
	);
}

/*
 *	读prefetch fault status register
 */
unsigned int read_prefetch_fsr()
{
	unsigned int reg;
	asm volatile(
		"mrc p15,0,r0,c5,c0,1 \n\t"
		"str r0,%0 \n\t"
		:
		:"mem"(reg)
		:"r0"
	);
	return reg;
}

/*
 *	写prefetch fault status register
 */
void write_prefetch_fsr(unsigned int reg)
{
	asm volatile(
		"ldr r0,%0 \n\t"
		"mcr p15,0,r0,c5,c0,1 \n\t"
		:
		:"mem"(reg)
		:"r0"
	);
}

/*
 *	读取 fault address register
 */
unsigned int read_far()
{
	unsigned int reg;
	asm volatile(
		"mrc p15,0,r0,c6,c0,0 \n\t"
		"str r0,%0 \n\t"
		:
		:"mem"(reg)
		:"r0"
	);
	return reg;
}
/*
 *	写fault address register
 */
void write_far(unsigned int reg)
{
	asm volatile(
		"ldr r0,%0 \n\t"
		"mcr p15,0,r0,c6,c0,0 \n\t"
		:
		:"mem"(reg)
		:"r0"
	);
}

/*
 *	使I TLB和 D TLB无效
 */
void invalidate_TLBs()
{
	asm volatile(
		"ldr r0,=0x00000000 \n\t"
		"mcr p15,0,r0,c8,c7,0 \n\t"
		:
		:
		:"r0"
	);	
}
/*
 *	使 D TLB无效
 */
void invalidate_DTLB()
{
	asm volatile(
		"ldr r0,=0x00000000 \n\t"
		"mcr p15,0,r0,c8,c6,0 \n\t"
		:
		:
		:"r0"
	);	
}
/*
 *	使 I TLB无效
 */
void invalidate_ITLB()
{
	asm volatile(
		"ldr r0,=0x00000000 \n\t"
		"mcr p15,0,r0,c8,c5,0 \n\t"
		:
		:
		:"r0"
	);	
}

/*
 *	使 DCache无效
 */
void invalidate_DCache()
{
	asm volatile(
		"ldr r0,=0x00000000 \n\t"
		"MCR p15,0,r0,c7,c6,0 \n\t"
		:
		:
		:"r0"
	);	
}


unsigned int get_process_id()
{
	unsigned int reg;
	asm volatile(
		"mrc p15,0,r0,c13,c0,0 \n\t" //read process identifier
		"str r0,%0 \n\t"
		:
		:"mem"(reg)
		:"r0"
	);
	return (reg>>25);	
}

void set_process_id(unsigned int reg)
{
	unsigned int tmp=reg<<25;
	asm volatile(
		"ldr r0,%0 \n\t"
		"mcr p15,0,r0,c13,c0,0 \n\t" //write process identifier
		:
		:"mem"(tmp)
		:"r0"
	);	
}