io.c

os arm os arm os arm os arm os arm os arm os arm os arm os arm os arm os arm os arm os arm os arm

/*
 *	ApOS (Another Project software for s3c2410)
 *	
 *	This program is free software; you can redistribute it and/or modify
 *	it under the terms of the GNU General Public License version 2 as
 *	published by the Free Software Foundation.
 *			
 *						Copyright caiyuqing
 *
 */
#include "../include/s3c2410/s3c2410.h"
#include "../include/s3c2410/io.h"
#include "../include/s3c2410/UDA1341TS.h" 


unsigned char port_io(char operate,unsigned char port_sel,
	unsigned char offset,unsigned  char data);

struct io_control_obj io_control_obj;

void io_control_obj_init(struct io_control_obj *ioco)
{
	ioco->gpa_con	=&rGPACON;
	ioco->gpa_data	=&rGPADAT;
                        
	ioco->gpb_con	=&rGPBCON;
	ioco->gpb_data	=&rGPBDAT;
	ioco->gpb_up	=&rGPBUP;
	
	ioco->gpc_con	=&rGPCCON;
	ioco->gpc_data	=&rGPCDAT;
	ioco->gpc_up	=&rGPCUP;

	ioco->gpd_con	=&rGPDCON;
	ioco->gpd_data	=&rGPDDAT;
	ioco->gpd_up	=&rGPDUP;

	ioco->gpe_con	=&rGPECON;
	ioco->gpe_data	=&rGPEDAT;
	ioco->gpe_up	=&rGPEUP;

	ioco->gpf_con	=&rGPFCON;
	ioco->gpf_data	=&rGPFDAT;
	ioco->gpf_up	=&rGPFUP;

	ioco->gpg_con	=&rGPGCON;
	ioco->gpg_data	=&rGPGDAT;
	ioco->gpg_up	=&rGPGUP;

	ioco->gph_con	=&rGPHCON;
	ioco->gph_data	=&rGPHDAT;
	ioco->gph_up	=&rGPHUP;
	
	ioco->misccr	=&rMISCCR;
	ioco->dclkcon	=&rDCLKCON;
	ioco->extint0	=&rEXTINT0;
	ioco->extint1	=&rEXTINT1;
	ioco->extint2	=&rEXTINT2;
	ioco->eintflt0	=&rEINTFLT0;
	ioco->eintflt1	=&rEINTFLT1;
	ioco->eintflt2	=&rEINTFLT2;
	ioco->eintflt3	=&rEINTFLT3;
	ioco->eintmask	=&rEINTMASK;
	ioco->eintpend	=&rEINTPEND;
	ioco->gstatus0	=&rGSTATUS0;
	ioco->gstatus1	=&rGSTATUS1;
	ioco->gstatus2	=&rGSTATUS2;
	ioco->gstatus3	=&rGSTATUS3;
	ioco->gstatus4	=&rGSTATUS4;
}
/*

*/
void io_config()
{
	/*
		PORT B GROUP
		Ports   : GPB15    GPB14    GPB13    GPB12    GPB11    GPB10    GPB9     GPB8     GPB7     GPB6    
		function: Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
		Binary  : 11	   11	    11	     11	      11       11	11	 11	  11	   11
   		-----------------------------------------------------------------------------------------
		Ports   : GPB5	   ?GPB4     GPB3     GPB2    GPB1	GPB0
		function: Reserved ?Output   Output   Output  Reserved 	Reserved
		Binary  : 11	   ?01	    01	     01	     11	        11
	*/
	set_port(PORT_B,0xFFFFFD5F,0,0xffff);

	set_port(PORT_C,0xAAAAAAAA,0,0xffff);

	set_port(PORT_D,0xAAAAAAAA,0,0xffff);
	
	/*
		PORT E GROUP
		Ports   : GPE15    GPE14    GPE13 	GPE12 	 GPE11    GPE10    GPE9     GPE8     GPE7       GPE6    
		function: Reserved Reserved Reserved	Reserved Reserved SDDAT3   SDDAT2   SDDAT1   SDDAT0	SDCMD
		Binary  : 11	   11	    11		11	 11	  10	   10	    10	     10		10
   		-----------------------------------------------------------------------------------------
		Ports   : GPE5	GPE4    GPE3   GPE2  GPE1    GPE0
		function: SDCLK	I2SSDO  I2SSDI CDCLK I2SSCLK I2SLRCK
		Binary  : 10	10	10     10    10	     10
	*/
	set_port(PORT_E,0xFFEAAAAA,0,0xffff);
	
	/*
		PORT F GROUP
		Ports   : GPG15    GPG14    GPG13    GPG12    GPG11    GPG10    GPG9     GPG8     GPG7     GPG6    
		function: Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
		Binary  : 11	   11	    11	     11	      11       11	11	 11	  01       11
   		-----------------------------------------------------------------------------------------
		Ports   : GPG5     GPG4     GPG3     GPG2     GPG1     GPG0
		function: Reserved Reserved Reserved Reserved Reserved EINT0
		Binary  : 11         01     11       11       11       10
	*/
	set_port(PORT_F,0xFFFF7DFE,0,0xffff);
	setup_eint(EINT0,SIG_METHOD_FAL_EDGE_TRIG,0);
	
	/*
		PORT G GROUP
		Ports   : GPG15  GPG14 GPG13 GPG12 GPG11   GPG10    GPG9     GPG8     GPG7      GPG6    
		function: nYPON  YMON  nXPON XMON  EINT19  EINT18   EINT17   EINT16   EINT15    EINT14
		Binary  : 11     11    11    11    10      10       10       10       10        10
   		-----------------------------------------------------------------------------------------
		Ports   : GPG5       GPG4    	GPG3    GPG2    GPG1    GPG0
		function: EINT113    LCD_PWRDN  EINT11  EINT10  EINT9   EINT8
		Binary  : 10         11     	10      10    	10      10
	*/
	set_port(PORT_G,0xFFAAABAA,0,0xFFFF);
	
	/*
		PORT H GROUP
		Ports   : GPG10	   GPG9     GPG8     GPG7      GPG6    
		function: CLKOUT1  CLKOUT0  UCLK     nCTS1     nRTS1
		Binary  : 10	   10	    10	     11	       11
   		-----------------------------------------------------------------------------------------
		Ports   : GPG5	GPG4	GPG3	GPG2	GPG1	GPG0
		function: RXD1  TXD1	RXD0	TXD0 	nRTS0	nCTS0
		Binary  : 10	10	10	10	10	10
	
	*/
	set_port(PORT_H,0x2AFAAA,0,0x7FF);
}

void set_port(unsigned char port_sel,
	unsigned int  con_val,unsigned int data_val,unsigned int up_val)
{
	switch(port_sel)
	{
		case PORT_A:
			*io_control_obj.gpa_con	=con_val;
			*io_control_obj.gpa_data=data_val;
			break;
			
		case PORT_B:
			*io_control_obj.gpb_con	=con_val;
			*io_control_obj.gpb_data=data_val;
			*io_control_obj.gpb_up	=up_val;		
			break;
			
		case PORT_C:
			*io_control_obj.gpc_con	=con_val;
			*io_control_obj.gpc_data=data_val;
			*io_control_obj.gpc_up	=up_val;			
			break;
			
		case PORT_D:
			*io_control_obj.gpd_con	=con_val;
			*io_control_obj.gpd_data=data_val;
			*io_control_obj.gpd_up	=up_val;			
			break;
			
		case PORT_E:
			*io_control_obj.gpe_con	=con_val;
			*io_control_obj.gpe_data=data_val;
			*io_control_obj.gpe_up	=up_val;			
			break;
			
		case PORT_F:
			*io_control_obj.gpf_con	=con_val;
			*io_control_obj.gpf_data=data_val;
			*io_control_obj.gpf_up	=up_val;			
			break;	
			
		case PORT_G:
			*io_control_obj.gpg_con	=con_val;
			*io_control_obj.gpg_data=data_val;
			*io_control_obj.gpg_up	=up_val;			
			break;	
			
		case PORT_H:
			*io_control_obj.gph_con	=con_val;
			*io_control_obj.gph_data=data_val;
			*io_control_obj.gph_up	=up_val;			
			break;	
			
	}
}

void setup_eint(unsigned char eint_x,
	unsigned char method,unsigned char filter)
{
	unsigned int reg;
	
	if(eint_x>=0&&eint_x<=7)
	{
		reg=*io_control_obj.extint0;
	}
	else if(eint_x>=8&&eint_x<=15)
	{
		reg=*io_control_obj.extint1;
	}
	else if(eint_x>=16&&eint_x<=23)
	{
		reg=*io_control_obj.extint2;
	}
	
	switch(eint_x)
	{
		case EINT23:  
			reg&=~(0x7<<28);
			reg|=(method&0x7)<<28;
			reg&=~(0x1<<31);
			reg|=(filter&1)<<31;
			break;
			
		case EINT22:  
			reg&=~(0x7<<24);
			reg|=(method&0x7)<<24;
			reg&=~(0x1<<27);
			reg|=(filter&1)<<27;
			break;
			
		case EINT21: 
			reg&=~(0x7<<20);
			reg|=(method&0x7)<<20;
			reg&=~(0x1<<23);
			reg|=(filter&1)<<23;
			break;
			
		case EINT20:			 
			reg&=~(0x7<<16);
			reg|=(method&0x7)<<16;
			reg&=~(0x1<<19);
			reg|=(filter&1)<<19;
			break;
			
		case EINT19: 
			reg&=~(0x7<<12);
			reg|=(method&0x7)<<12;
			reg&=~(0x1<<15);
			reg|=(filter&1)<<15;
			break;
			
		case EINT18: 
			reg&=~(0x7<<8);
			reg|=(method&0x7)<<8;
			reg&=~(0x1<<11);
			reg|=(filter&1)<<11;
			break;
			
		case EINT17: 
			reg&=~(0x7<<4);
			reg|=(method&0x7)<<4;
			reg&=~(0x1<<7);
			reg|=(filter&1)<<7;
			break;
			
		case EINT16: 
			reg&=~(0x7<<0);
			reg|=(method&0x7)<<0;
			reg&=~(0x1<<3);
			reg|=(filter&1)<<3;
			break;
			
		case EINT15: 
			reg&=~(0x7<<28);
			reg|=(method&0x7)<<28;
			break;
			
		case EINT14: 
			reg&=~(0x7<<24);
			reg|=(method&0x7)<<24;
			break;
			
		case EINT13: 
			reg&=~(0x7<<20);
			reg|=(method&0x7)<<20;
			break;
			
		case EINT12: 
			reg&=~(0x7<<16);
			reg|=(method&0x7)<<16;
			break;
			
		case EINT11: 
			reg&=~(0x7<<12);
			reg|=(method&0x7)<<12;
			break;
			
		case EINT10: 
			reg&=~(0x7<<8);
			reg|=(method&0x7)<<8;
			break;
			
		case EINT9: 
			reg&=~(0x7<<4);
			reg|=(method&0x7)<<4;
			break;
			
		case EINT8:
			reg&=~(0x7<<0);
			reg|=(method&0x7)<<0;
			break;
			
		case EINT7: 
			reg&=~(0x7<<28);
			reg|=(method&0x7)<<28;
			break;
			
		case EINT6: 
			reg&=~(0x7<<24);
			reg|=(method&0x7)<<24;
			break;
			
		case EINT5: 
			reg&=~(0x7<<20);
			reg|=(method&0x7)<<20;
			break;
			
		case EINT4: 
			reg&=~(0x7<<16);
			reg|=(method&0x7)<<16;
			break;
			
		case EINT3: 
			reg&=~(0x7<<12);
			reg|=(method&0x7)<<12;
			break;
			
		case EINT2: 
			reg&=~(0x7<<8);
			reg|=(method&0x7)<<8;
			break;
			
		case EINT1:  
			reg&=~(0x7<<4);
			reg|=(method&0x7)<<4;
			break;
			
		case EINT0: 
			reg&=~(0x7<<0);
			reg|=(method&0x7)<<0;
			break;
			
	}
	
	if(eint_x>=0&&eint_x<=7)
	{
		*io_control_obj.extint0=reg;
	}
	else if(eint_x>=8&&eint_x<=15)
	{
		*io_control_obj.extint1=reg;
	}
	else if(eint_x>=16&&eint_x<=23)
	{
		*io_control_obj.extint2=reg;
	}
	
}

unsigned char port_io(char operate,unsigned char port_sel,
	unsigned char offset,unsigned  char data)
{
	unsigned short data_reg;
	data_reg=*(io_control_obj.gpa_data+(port_sel*0x10));
	
	switch(operate)
	{
		case IO_IN:
			return (data_reg>>offset)&0x1;
						
		case IO_OUT:
			data_reg&=~(1<<offset);
			data_reg|=(data<<offset);
			*(io_control_obj.gpa_data+(port_sel*0x10))=data_reg;

			return 1;
			
	}
	
}