📄 csl_emifahal.h
字号:
* (rw) RFEN
* (w) INIT
* (rw) TRCD
* (rw) TRP
* (rw) TRC
* (rw) SLFRFR
*
\******************************************************************************/
#define _EMIFA_SDCTL_OFFSET 6
#define _EMIFA_SDCTL_ADDR 0x01800018u
#define _EMIFA_SDCTL_SDBSZ_MASK 0x40000000u
#define _EMIFA_SDCTL_SDBSZ_SHIFT 0x0000001Eu
#define EMIFA_SDCTL_SDBSZ_DEFAULT 0x00000000u
#define EMIFA_SDCTL_SDBSZ_OF(x) _VALUEOF(x)
#define EMIFA_SDCTL_SDBSZ_2BANKS 0x00000000u
#define EMIFA_SDCTL_SDBSZ_4BANKS 0x00000001u
#define _EMIFA_SDCTL_SDRSZ_MASK 0x30000000u
#define _EMIFA_SDCTL_SDRSZ_SHIFT 0x0000001Cu
#define EMIFA_SDCTL_SDRSZ_DEFAULT 0x00000000u
#define EMIFA_SDCTL_SDRSZ_OF(x) _VALUEOF(x)
#define EMIFA_SDCTL_SDRSZ_11ROW 0x00000000u
#define EMIFA_SDCTL_SDRSZ_12ROW 0x00000001u
#define EMIFA_SDCTL_SDRSZ_13ROW 0x00000002u
#define _EMIFA_SDCTL_SDCSZ_MASK 0x0C000000u
#define _EMIFA_SDCTL_SDCSZ_SHIFT 0x0000001Au
#define EMIFA_SDCTL_SDCSZ_DEFAULT 0x00000000u
#define EMIFA_SDCTL_SDCSZ_OF(x) _VALUEOF(x)
#define EMIFA_SDCTL_SDCSZ_9COL 0x00000000u
#define EMIFA_SDCTL_SDCSZ_8COL 0x00000001u
#define EMIFA_SDCTL_SDCSZ_10COL 0x00000002u
#define _EMIFA_SDCTL_RFEN_MASK 0x02000000u
#define _EMIFA_SDCTL_RFEN_SHIFT 0x00000019u
#define EMIFA_SDCTL_RFEN_DEFAULT 0x00000001u
#define EMIFA_SDCTL_RFEN_OF(x) _VALUEOF(x)
#define EMIFA_SDCTL_RFEN_DISABLE 0x00000000u
#define EMIFA_SDCTL_RFEN_ENABLE 0x00000001u
#define _EMIFA_SDCTL_INIT_MASK 0x01000000u
#define _EMIFA_SDCTL_INIT_SHIFT 0x00000018u
#define EMIFA_SDCTL_INIT_DEFAULT 0x00000001u
#define EMIFA_SDCTL_INIT_OF(x) _VALUEOF(x)
#define EMIFA_SDCTL_INIT_NO 0x00000000u
#define EMIFA_SDCTL_INIT_YES 0x00000001u
#define _EMIFA_SDCTL_TRCD_MASK 0x00F00000u
#define _EMIFA_SDCTL_TRCD_SHIFT 0x00000014u
#define EMIFA_SDCTL_TRCD_DEFAULT 0x00000004u
#define EMIFA_SDCTL_TRCD_OF(x) _VALUEOF(x)
#define _EMIFA_SDCTL_TRP_MASK 0x000F0000u
#define _EMIFA_SDCTL_TRP_SHIFT 0x00000010u
#define EMIFA_SDCTL_TRP_DEFAULT 0x00000008u
#define EMIFA_SDCTL_TRP_OF(x) _VALUEOF(x)
#define _EMIFA_SDCTL_TRC_MASK 0x0000F000u
#define _EMIFA_SDCTL_TRC_SHIFT 0x0000000Cu
#define EMIFA_SDCTL_TRC_DEFAULT 0x0000000Fu
#define EMIFA_SDCTL_TRC_OF(x) _VALUEOF(x)
#define _EMIFA_SDCTL_SLFRFR_MASK 0x00000001u
#define _EMIFA_SDCTL_SLFRFR_SHIFT 0x00000000u
#define EMIFA_SDCTL_SLFRFR_DEFAULT 0x00000000u
#define EMIFA_SDCTL_SLFRFR_OF(x) _VALUEOF(x)
#define EMIFA_SDCTL_SLFRFR_DISABLE 0x00000000u
#define EMIFA_SDCTL_SLFRFR_ENABLE 0x00000001u
#define EMIFA_SDCTL_OF(x) _VALUEOF(x)
#define EMIFA_SDCTL_DEFAULT (Uint32)( \
_PER_FDEFAULT(EMIFA,SDCTL,SDBSZ)\
|_PER_FDEFAULT(EMIFA,SDCTL,SDRSZ)\
|_PER_FDEFAULT(EMIFA,SDCTL,SDCSZ)\
|_PER_FDEFAULT(EMIFA,SDCTL,RFEN)\
|_PER_FDEFAULT(EMIFA,SDCTL,INIT)\
|_PER_FDEFAULT(EMIFA,SDCTL,TRCD)\
|_PER_FDEFAULT(EMIFA,SDCTL,TRP)\
|_PER_FDEFAULT(EMIFA,SDCTL,TRC)\
|_PER_FDEFAULT(EMIFA,SDCTL,SLFRFR)\
)
#define EMIFA_SDCTL_RMK(sdbsz,sdrsz,sdcsz,rfen,init,trcd,trp,trc,slfrfr) (Uint32)(\
_PER_FMK(EMIFA,SDCTL,SDBSZ,sdbsz)\
|_PER_FMK(EMIFA,SDCTL,SDRSZ,sdrsz)\
|_PER_FMK(EMIFA,SDCTL,SDCSZ,sdcsz)\
|_PER_FMK(EMIFA,SDCTL,RFEN,rfen)\
|_PER_FMK(EMIFA,SDCTL,INIT,init)\
|_PER_FMK(EMIFA,SDCTL,TRCD,trcd)\
|_PER_FMK(EMIFA,SDCTL,TRP,trp)\
|_PER_FMK(EMIFA,SDCTL,TRC,trc)\
|_PER_FMK(EMIFA,SDCTL,SLFRFR,slfrfr)\
)
#define _EMIFA_SDCTL_FGET(FIELD)\
_PER_FGET(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD)
#define _EMIFA_SDCTL_FSET(FIELD,field)\
_PER_FSET(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD,field)
#define _EMIFA_SDCTL_FSETS(FIELD,SYM)\
_PER_FSETS(_EMIFA_SDCTL_ADDR,EMIFA,SDCTL,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | S D T I M |
* |___________________|
*
* SDTIM - SDRAM timing register
*
* FIELDS (msb -> lsb)
* (rw) XRFR
* (r) CNTR
* (rw) PERIOD
*
\******************************************************************************/
#define _EMIFA_SDTIM_OFFSET 7
#define _EMIFA_SDTIM_ADDR 0x0180001Cu
#define _EMIFA_SDTIM_XRFR_MASK 0x03000000u
#define _EMIFA_SDTIM_XRFR_SHIFT 0x00000018u
#define EMIFA_SDTIM_XRFR_DEFAULT 0x00000000u
#define EMIFA_SDTIM_XRFR_OF(x) _VALUEOF(x)
#define _EMIFA_SDTIM_CNTR_MASK 0x00FFF000u
#define _EMIFA_SDTIM_CNTR_SHIFT 0x0000000Cu
#define EMIFA_SDTIM_CNTR_DEFAULT 0x000005DCu
#define EMIFA_SDTIM_CNTR_OF(x) _VALUEOF(x)
#define _EMIFA_SDTIM_PERIOD_MASK 0x00000FFFu
#define _EMIFA_SDTIM_PERIOD_SHIFT 0x00000000u
#define EMIFA_SDTIM_PERIOD_DEFAULT 0x000005DCu
#define EMIFA_SDTIM_PERIOD_OF(x) _VALUEOF(x)
#define EMIFA_SDTIM_OF(x) _VALUEOF(x)
#define EMIFA_SDTIM_DEFAULT (Uint32)( \
_PER_FDEFAULT(EMIFA,SDTIM,XRFR)\
|_PER_FDEFAULT(EMIFA,SDTIM,CNTR)\
|_PER_FDEFAULT(EMIFA,SDTIM,PERIOD)\
)
#define EMIFA_SDTIM_RMK(xrfr,period) (Uint32)(\
_PER_FMK(EMIFA,SDTIM,XRFR,xrfr)\
|_PER_FMK(EMIFA,SDTIM,PERIOD,period)\
)
#define _EMIFA_SDTIM_FGET(FIELD)\
_PER_FGET(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD)
#define _EMIFA_SDTIM_FSET(FIELD,field)\
_PER_FSET(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD,field)
#define _EMIFA_SDTIM_FSETS(FIELD,SYM)\
_PER_FSETS(_EMIFA_SDTIM_ADDR,EMIFA,SDTIM,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | S D E X T |
* |___________________|
*
* SDEXT - SDRAM extension register
*
* FIELDS (msb -> lsb)
* (rw) WR2RD
* (rw) WR2DEAC
* (rw) WR2WR
* (rw) R2WDQM
* (rw) RD2WR
* (rw) RD2DEAC
* (rw) RD2RD
* (rw) THZP
* (rw) TWR
* (rw) TRRD
* (rw) TRAS
* (rw) TCL
*
\******************************************************************************/
#define _EMIFA_SDEXT_OFFSET 8
#define _EMIFA_SDEXT_ADDR 0x01800020u
#define _EMIFA_SDEXT_WR2RD_MASK 0x00100000u
#define _EMIFA_SDEXT_WR2RD_SHIFT 0x00000014u
#define EMIFA_SDEXT_WR2RD_DEFAULT 0x00000001u
#define EMIFA_SDEXT_WR2RD_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_WR2DEAC_MASK 0x000C0000u
#define _EMIFA_SDEXT_WR2DEAC_SHIFT 0x00000012u
#define EMIFA_SDEXT_WR2DEAC_DEFAULT 0x00000001u
#define EMIFA_SDEXT_WR2DEAC_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_WR2WR_MASK 0x00020000u
#define _EMIFA_SDEXT_WR2WR_SHIFT 0x00000011u
#define EMIFA_SDEXT_WR2WR_DEFAULT 0x00000001u
#define EMIFA_SDEXT_WR2WR_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_R2WDQM_MASK 0x00018000u
#define _EMIFA_SDEXT_R2WDQM_SHIFT 0x0000000Fu
#define EMIFA_SDEXT_R2WDQM_DEFAULT 0x00000002u
#define EMIFA_SDEXT_R2WDQM_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_RD2WR_MASK 0x00007000u
#define _EMIFA_SDEXT_RD2WR_SHIFT 0x0000000Cu
#define EMIFA_SDEXT_RD2WR_DEFAULT 0x00000005u
#define EMIFA_SDEXT_RD2WR_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_RD2DEAC_MASK 0x00000C00u
#define _EMIFA_SDEXT_RD2DEAC_SHIFT 0x0000000Au
#define EMIFA_SDEXT_RD2DEAC_DEFAULT 0x00000003u
#define EMIFA_SDEXT_RD2DEAC_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_RD2RD_MASK 0x00000200u
#define _EMIFA_SDEXT_RD2RD_SHIFT 0x00000009u
#define EMIFA_SDEXT_RD2RD_DEFAULT 0x00000001u
#define EMIFA_SDEXT_RD2RD_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_THZP_MASK 0x00000180u
#define _EMIFA_SDEXT_THZP_SHIFT 0x00000007u
#define EMIFA_SDEXT_THZP_DEFAULT 0x00000002u
#define EMIFA_SDEXT_THZP_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_TWR_MASK 0x00000060u
#define _EMIFA_SDEXT_TWR_SHIFT 0x00000005u
#define EMIFA_SDEXT_TWR_DEFAULT 0x00000001u
#define EMIFA_SDEXT_TWR_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_TRRD_MASK 0x00000010u
#define _EMIFA_SDEXT_TRRD_SHIFT 0x00000004u
#define EMIFA_SDEXT_TRRD_DEFAULT 0x00000001u
#define EMIFA_SDEXT_TRRD_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_TRAS_MASK 0x0000000Eu
#define _EMIFA_SDEXT_TRAS_SHIFT 0x00000001u
#define EMIFA_SDEXT_TRAS_DEFAULT 0x00000007u
#define EMIFA_SDEXT_TRAS_OF(x) _VALUEOF(x)
#define _EMIFA_SDEXT_TCL_MASK 0x00000001u
#define _EMIFA_SDEXT_TCL_SHIFT 0x00000000u
#define EMIFA_SDEXT_TCL_DEFAULT 0x00000001u
#define EMIFA_SDEXT_TCL_OF(x) _VALUEOF(x)
#define EMIFA_SDEXT_OF(x) _VALUEOF(x)
#define EMIFA_SDEXT_DEFAULT (Uint32)( \
_PER_FDEFAULT(EMIFA,SDEXT,WR2RD)\
|_PER_FDEFAULT(EMIFA,SDEXT,WR2DEAC)\
|_PER_FDEFAULT(EMIFA,SDEXT,WR2WR)\
|_PER_FDEFAULT(EMIFA,SDEXT,R2WDQM)\
|_PER_FDEFAULT(EMIFA,SDEXT,RD2WR)\
|_PER_FDEFAULT(EMIFA,SDEXT,RD2DEAC)\
|_PER_FDEFAULT(EMIFA,SDEXT,RD2RD)\
|_PER_FDEFAULT(EMIFA,SDEXT,THZP)\
|_PER_FDEFAULT(EMIFA,SDEXT,TWR)\
|_PER_FDEFAULT(EMIFA,SDEXT,TRRD)\
|_PER_FDEFAULT(EMIFA,SDEXT,TRAS)\
|_PER_FDEFAULT(EMIFA,SDEXT,TCL)\
)
#define EMIFA_SDEXT_RMK(wr2rd,wr2deac,wr2wr,r2wdqm,rd2wr,rd2deac,\
rd2rd,thzp,twr,trrd,tras,tcl) (Uint32)( \
_PER_FMK(EMIFA,SDEXT,WR2RD,wr2rd)\
|_PER_FMK(EMIFA,SDEXT,WR2DEAC,wr2deac)\
|_PER_FMK(EMIFA,SDEXT,WR2WR,wr2wr)\
|_PER_FMK(EMIFA,SDEXT,R2WDQM,r2wdqm)\
|_PER_FMK(EMIFA,SDEXT,RD2WR,rd2wr)\
|_PER_FMK(EMIFA,SDEXT,RD2DEAC,rd2deac)\
|_PER_FMK(EMIFA,SDEXT,RD2RD,rd2rd)\
|_PER_FMK(EMIFA,SDEXT,THZP,thzp)\
|_PER_FMK(EMIFA,SDEXT,TWR,twr)\
|_PER_FMK(EMIFA,SDEXT,TRRD,trrd)\
|_PER_FMK(EMIFA,SDEXT,TRAS,tras)\
|_PER_FMK(EMIFA,SDEXT,TCL,tcl)\
)
#define _EMIFA_SDEXT_FGET(FIELD)\
_PER_FGET(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD)
#define _EMIFA_SDEXT_FSET(FIELD,field)\
_PER_FSET(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD,field)
#define _EMIFA_SDEXT_FSETS(FIELD,SYM)\
_PER_FSETS(_EMIFA_SDEXT_ADDR,EMIFA,SDEXT,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | C E x S E C |
* |___________________|
*
* CESEC0 - CE space secondary control register 0
* CESEC1 - CE space secondary control register 1
* CESEC2 - CE space secondary control register 2
* CESEC3 - CE space secondary control register 3
*
* FIELDS (msb -> lsb)
* (rw) SNCCLK
* (rw) RENEN
* (rw) CEEXT
* (rw) SYNCWL
* (rw) SYNCRL
*
\******************************************************************************/
#define _EMIFA_CESEC0_OFFSET 18
#define _EMIFA_CESEC1_OFFSET 17
#define _EMIFA_CESEC2_OFFSET 20
#define _EMIFA_CESEC3_OFFSET 21
#define _EMIFA_CESEC0_ADDR 0x01800048u
#define _EMIFA_CESEC1_ADDR 0x01800044u
#define _EMIFA_CESEC2_ADDR 0x01800050u
#define _EMIFA_CESEC3_ADDR 0x01800054u
#define _EMIFA_CESEC_SNCCLK_MASK 0x00000040u
#define _EMIFA_CESEC_SNCCLK_SHIFT 0x00000006u
#define EMIFA_CESEC_SNCCLK_DEFAULT 0x00000000u
#define EMIFA_CESEC_SNCCLK_OF(x) _VALUEOF(x)
#define EMIFA_CESEC_SNCCLK_ECLKOUT1 0x00000000u
#define EMIFA_CESEC_SNCCLK_ECLKOUT2 0x00000001u
#define _EMIFA_CESEC_RENEN_MASK 0x00000020u
#define _EMIFA_CESEC_RENEN_SHIFT 0x00000005u
#define EMIFA_CESEC_RENEN_DEFAULT 0x00000000u
#define EMIFA_CESEC_RENEN_OF(x) _VALUEOF(x)
#define EMIFA_CESEC_RENEN_ADS 0x00000000u
#define EMIFA_CESEC_RENEN_READ 0x00000001u
#define _EMIFA_CESEC_CEEXT_MASK 0x00000010u
#define _EMIFA_CESEC_CEEXT_SHIFT 0x00000004u
#define EMIFA_CESEC_CEEXT_DEFAULT 0x00000000u
#define EMIFA_CESEC_CEEXT_OF(x) _VALUEOF(x)
#define EMIFA_CESEC_CEEXT_INACTIVE 0x00000000u
#define EMIFA_CESEC_CEEXT_ACTIVE 0x00000001u
#define _EMIFA_CESEC_SYNCWL_MASK 0x0000000Cu
#define _EMIFA_CESEC_SYNCWL_SHIFT 0x00000002u
#define EMIFA_CESEC_SYNCWL_DEFAULT 0x00000000u
#define EMIFA_CESEC_SYNCWL_OF(x) _VALUEOF(x)
#define EMIFA_CESEC_SYNCWL_0CYCLE 0x00000000u
#define EMIFA_CESEC_SYNCWL_1CYCLE 0x00000001u
#define EMIFA_CESEC_SYNCWL_2CYCLE 0x00000002u
#define EMIFA_CESEC_SYNCWL_3CYCLE 0x00000003u
#define _EMIFA_CESEC_SYNCRL_MASK 0x00000003u
#define _EMIFA_CESEC_SYNCRL_SHIFT 0x00000000u
#define EMIFA_CESEC_SYNCRL_DEFAULT 0x00000002u
#define EMIFA_CESEC_SYNCRL_OF(x) _VALUEOF(x)
#define EMIFA_CESEC_SYNCRL_0CYCLE 0x00000000u
#define EMIFA_CESEC_SYNCRL_1CYCLE 0x00000001u
#define EMIFA_CESEC_SYNCRL_2CYCLE 0x00000002u
#define EMIFA_CESEC_SYNCRL_3CYCLE 0x00000003u
#define EMIFA_CESEC_OF(x) _VALUEOF(x)
#define EMIFA_CESEC_DEFAULT (Uint32)( \
_PER_FDEFAULT(EMIFA,CESEC,SNCCLK)\
|_PER_FDEFAULT(EMIFA,CESEC,RENEN)\
|_PER_FDEFAULT(EMIFA,CESEC,CEEXT)\
|_PER_FDEFAULT(EMIFA,CESEC,SYNCWL)\
|_PER_FDEFAULT(EMIFA,CESEC,SYNCRL)\
)
#define EMIFA_CESEC_RMK(sncclk,renen,ceext,syncwl,syncrl)\
(Uint32)( \
_PER_FMK(EMIFA,CESEC,SNCCLK,sncclk)\
|_PER_FMK(EMIFA,CESEC,RENEN,renen)\
|_PER_FMK(EMIFA,CESEC,CEEXT,ceext)\
|_PER_FMK(EMIFA,CESEC,SYNCWL,syncwl)\
|_PER_FMK(EMIFA,CESEC,SYNCRL,syncrl)\
)
#define _EMIFA_CESEC_FGET(N,FIELD)\
_PER_FGET(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD)
#define _EMIFA_CESEC_FSET(N,FIELD,f)\
_PER_FSET(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD,f)
#define _EMIFA_CESEC_FSETS(N,FIELD,SYM)\
_PER_FSETS(_EMIFA_CESEC##N##_ADDR,EMIFA,CESEC,##FIELD,##SYM)
#define _EMIFA_CESEC0_FGET(FIELD) _EMIFA_CESEC_FGET(0,##FIELD)
#define _EMIFA_CESEC1_FGET(FIELD) _EMIFA_CESEC_FGET(1,##FIELD)
#define _EMIFA_CESEC2_FGET(FIELD) _EMIFA_CESEC_FGET(2,##FIELD)
#define _EMIFA_CESEC3_FGET(FIELD) _EMIFA_CESEC_FGET(3,##FIELD)
#define _EMIFA_CESEC0_FSET(FIELD,f) _EMIFA_CESEC_FSET(0,##FIELD,f)
#define _EMIFA_CESEC1_FSET(FIELD,f) _EMIFA_CESEC_FSET(1,##FIELD,f)
#define _EMIFA_CESEC2_FSET(FIELD,f) _EMIFA_CESEC_FSET(2,##FIELD,f)
#define _EMIFA_CESEC3_FSET(FIELD,f) _EMIFA_CESEC_FSET(3,##FIELD,f)
#define _EMIFA_CESEC0_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(0,##FIELD,##SYM)
#define _EMIFA_CESEC1_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(1,##FIELD,##SYM)
#define _EMIFA_CESEC2_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(2,##FIELD,##SYM)
#define _EMIFA_CESEC3_FSETS(FIELD,SYM) _EMIFA_CESEC_FSETS(3,##FIELD,##SYM)
#endif /* EMIFA_SUPPORT */
#endif /* _CSL_EMIFHAL_H_ */
/******************************************************************************\
* End of csl_emifahal.h
\******************************************************************************/
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