csl_legacyhal.h

SEED的VPM642测试程序-板级支持库

\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF8_MASK                     (0x00000100)
  #define HCHIP_IFR_IF8_SHIFT                    (0x00000008)

  #define HCHIP_IFR_IF8_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF8)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF9
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF9_MASK                     (0x00000200)
  #define HCHIP_IFR_IF9_SHIFT                    (0x00000009)

  #define HCHIP_IFR_IF9_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF9)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF10
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF10_MASK                    (0x00000400)
  #define HCHIP_IFR_IF10_SHIFT                   (0x0000000A)

  #define HCHIP_IFR_IF10_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF10)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF11
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF11_MASK                    (0x00000800)
  #define HCHIP_IFR_IF11_SHIFT                   (0x0000000B)

  #define HCHIP_IFR_IF11_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF11)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF12
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF12_MASK                    (0x00001000)
  #define HCHIP_IFR_IF12_SHIFT                   (0x0000000C)

  #define HCHIP_IFR_IF12_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF12)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF13
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF13_MASK                    (0x00002000)
  #define HCHIP_IFR_IF13_SHIFT                   (0x0000000D)

  #define HCHIP_IFR_IF13_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF13)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF14
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF14_MASK                    (0x00004000)
  #define HCHIP_IFR_IF14_SHIFT                   (0x0000000E)

  #define HCHIP_IFR_IF14_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF14)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR_IF15
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_IF15_MASK                    (0x00008000)
  #define HCHIP_IFR_IF15_SHIFT                   (0x0000000F)

  #define HCHIP_IFR_IF15_GET(CrReg) \
    HCRFIELD_GET(CrReg,HCHIP_IFR_IF15)

/*----------------------------------------------------------------------------*\
* (R) HCHIP_IFR
\*----------------------------------------------------------------------------*/
  #define HCHIP_IFR_GET(CrReg) HCRREG32_GET(CrReg)

/******************************************************************************\
* HCHIP_ISR - interrupt set register
*
* Fields:
*   (W)  HCHIP_ISR_IS4
*   (W)  HCHIP_ISR_IS5
*   (W)  HCHIP_ISR_IS6
*   (W)  HCHIP_ISR_IS7
*   (W)  HCHIP_ISR_IS8
*   (W)  HCHIP_ISR_IS9
*   (W)  HCHIP_ISR_IS10
*   (W)  HCHIP_ISR_IS11
*   (W)  HCHIP_ISR_IS12
*   (W)  HCHIP_ISR_IS13
*   (W)  HCHIP_ISR_IS14
*   (W)  HCHIP_ISR_IS15
*
\******************************************************************************/
  extern far cregister volatile unsigned int ISR;
  #define HCHIP_ISR ISR

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS4
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS4_MASK                     (0x00000010)
  #define HCHIP_ISR_IS4_SHIFT                    (0x00000004)

  #define HCHIP_ISR_IS4_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS4,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS5
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS5_MASK                     (0x00000020)
  #define HCHIP_ISR_IS5_SHIFT                    (0x00000005)

  #define HCHIP_ISR_IS5_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS5,Val))
    
/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS6
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS6_MASK                     (0x00000040)
  #define HCHIP_ISR_IS6_SHIFT                    (0x00000006)

  #define HCHIP_ISR_IS6_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS6,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS7
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS7_MASK                     (0x00000080)
  #define HCHIP_ISR_IS7_SHIFT                    (0x00000007)

  #define HCHIP_ISR_IS7_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS7,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS8
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS8_MASK                     (0x00000100)
  #define HCHIP_ISR_IS8_SHIFT                    (0x00000008)

  #define HCHIP_ISR_IS8_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS8,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS9
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS9_MASK                     (0x00000200)
  #define HCHIP_ISR_IS9_SHIFT                    (0x00000009)

  #define HCHIP_ISR_IS9_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS9,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS10
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS10_MASK                    (0x00000400)
  #define HCHIP_ISR_IS10_SHIFT                   (0x0000000A)

  #define HCHIP_ISR_IS10_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS10,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS11
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS11_MASK                    (0x00000800)
  #define HCHIP_ISR_IS11_SHIFT                   (0x0000000B)

  #define HCHIP_ISR_IS11_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS11,Val))
/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS12
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS12_MASK                    (0x00001000)
  #define HCHIP_ISR_IS12_SHIFT                   (0x0000000C)

  #define HCHIP_ISR_IS12_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS12,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS13
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS13_MASK                    (0x00002000)
  #define HCHIP_ISR_IS13_SHIFT                   (0x0000000D)

  #define HCHIP_ISR_IS13_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS13,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS14
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS14_MASK                    (0x00004000)
  #define HCHIP_ISR_IS14_SHIFT                   (0x0000000E)

  #define HCHIP_ISR_IS14_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS14,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR_IS15
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_IS15_MASK                    (0x00008000)
  #define HCHIP_ISR_IS15_SHIFT                   (0x0000000F)

  #define HCHIP_ISR_IS15_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ISR_IS15,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ISR
\*----------------------------------------------------------------------------*/
  #define HCHIP_ISR_SET(CrReg,Val) HCRREG32_SET(CrReg,Val)

  #define HCHIP_ISR_CFG(CrReg,is4,is5,is6,is7,is8,is9,is10,is11,is12,is13,is14,\
  is15) CrReg=(UINT32)( \
      HCRFIELD_SHIFT(HCHIP_ISR_IS4, is4) |\
      HCRFIELD_SHIFT(HCHIP_ISR_IS5, is5) |\
      HCRFIELD_SHIFT(HCHIP_ISR_IS6, is6) |\
      HCRFIELD_SHIFT(HCHIP_ISR_IS7, is7) |\
      HCRFIELD_SHIFT(HCHIP_ISR_IS8, is8) |\
      HCRFIELD_SHIFT(HCHIP_ISR_IS9, is9) |\
      HCRFIELD_SHIFT(HCHIP_ISR_IS10,is10)|\
      HCRFIELD_SHIFT(HCHIP_ISR_IS11,is11)|\
      HCRFIELD_SHIFT(HCHIP_ISR_IS12,is12)|\
      HCRFIELD_SHIFT(HCHIP_ISR_IS13,is13)|\
      HCRFIELD_SHIFT(HCHIP_ISR_IS14,is14)|\
      HCRFIELD_SHIFT(HCHIP_ISR_IS15,is15) \
    )   

/******************************************************************************\
* HCHIP_ICR - interrupt clear register
*
* Fields:
*   (W)  HCHIP_ICR_IC4
*   (W)  HCHIP_ICR_IC5
*   (W)  HCHIP_ICR_IC6
*   (W)  HCHIP_ICR_IC7
*   (W)  HCHIP_ICR_IC8
*   (W)  HCHIP_ICR_IC9
*   (W)  HCHIP_ICR_IC10
*   (W)  HCHIP_ICR_IC11
*   (W)  HCHIP_ICR_IC12
*   (W)  HCHIP_ICR_IC13
*   (W)  HCHIP_ICR_IC14
*   (W)  HCHIP_ICR_IC15
*
\******************************************************************************/
  extern far cregister volatile unsigned int ICR;
  #define HCHIP_ICR ICR

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC4
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC4_MASK                     (0x00000010)
  #define HCHIP_ICR_IC4_SHIFT                    (0x00000004)

  #define HCHIP_ICR_IC4_SET(CrReg,Val) \
  HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC4,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC5
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC5_MASK                     (0x00000020)
  #define HCHIP_ICR_IC5_SHIFT                    (0x00000005)

  #define HCHIP_ICR_IC5_SET(CrReg,Val) \
  HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC5,Val))
    

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC6
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC6_MASK                     (0x00000040)
  #define HCHIP_ICR_IC6_SHIFT                    (0x00000006)
  
  #define HCHIP_ICR_IC6_SET(CrReg,Val) \
   HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC6,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC7
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC7_MASK                     (0x00000080)
  #define HCHIP_ICR_IC7_SHIFT                    (0x00000007)

  #define HCHIP_ICR_IC7_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC7,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC8
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC8_MASK                     (0x00000100)
  #define HCHIP_ICR_IC8_SHIFT                    (0x00000008)

  #define HCHIP_ICR_IC8_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC8,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC9
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC9_MASK                     (0x00000200)
  #define HCHIP_ICR_IC9_SHIFT                    (0x00000009)

  #define HCHIP_ICR_IC9_SET(CrReg,Val) \
    HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC9,Val))

/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC10
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC10_MASK                    (0x00000400)
  #define HCHIP_ICR_IC10_SHIFT                   (0x0000000A)

  #define HCHIP_ICR_IC10_SET(CrReg,Val) \
  HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC10,Val))
  
/*----------------------------------------------------------------------------*\
* (W) HCHIP_ICR_IC11
\*----------------------------------------------------------------------------*/
  #define HCHIP_ICR_IC11_MASK                    (0x00000800)
  #define HCHIP_ICR_IC11_SHIFT                   (0x0000000B)

  #define HCHIP_ICR_IC11_SET(CrReg,Val) \
   HCRREG32_SET(CrReg,HFIELD_SHIFT(HCHIP_ICR_IC11,Val))
/*----------------------------------------------------------------------------*\