📄 csl_pcihal.h
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#define PCI_CDSPA_OF(x) _VALUEOF(x)
#define PCI_CDSPA_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,CDSPA,CDSPA) \
)
#define PCI_CDSPA_RMK(cdspa)\
(Uint32)( \
_PER_FMK(PCI,CDSPA,CDSPA,cdspa) \
)
#define _PCI_CDSPA_FGET(FIELD)\
_PER_FGET(_PCI_CDSPA_ADDR,PCI,CDSPA,##FIELD)
/******************************************************************************\
* _____________________
* | |
* | C P C I A |
* |___________________|
*
* CPCIA - Current PCI Address Register
*
* FIELDS (msb -> lsb)
* (r) CPCIA
*
\******************************************************************************/
#define _PCI_CPCIA_OFFSET 8
#if (C64_SUPPORT)
#define _PCI_CPCIA_ADDR 0x01C00020u
#else
#define _PCI_CPCIA_ADDR 0x01A40020u
#endif
#define _PCI_CPCIA_CPCIA_MASK 0xFFFFFFFFu
#define _PCI_CPCIA_CPCIA_SHIFT 0x00000000u
#define PCI_CPCIA_CPCIA_DEFAULT 0x00000000u
#define PCI_CPCIA_CPCIA_OF(x) _VALUEOF(x)
#define PCI_CPCIA_OF(x) _VALUEOF(x)
#define PCI_CPCIA_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,CPCIA,CPCIA) \
)
#define PCI_CPCIA_RMK(cpcia)\
(Uint32)( \
_PER_FMK(PCI,CPCIA,CPCIA,cpcia) \
)
#define _PCI_CPCIA_FGET(FIELD)\
_PER_FGET(_PCI_CPCIA_ADDR,PCI,CPCIA,##FIELD)
/******************************************************************************\
* _____________________
* | |
* | C C N T |
* |___________________|
*
* CCNT - Current Byte Counter Register
*
* FIELDS (msb -> lsb)
* (r) CCNT
*
\******************************************************************************/
#define _PCI_CCNT_OFFSET 9
#if (C64_SUPPORT)
#define _PCI_CCNT_ADDR 0x01C00024u
#else
#define _PCI_CCNT_ADDR 0x01A40024u
#endif
#define _PCI_CCNT_CCNT_MASK 0x0000FFFFu
#define _PCI_CCNT_CCNT_SHIFT 0x00000000u
#define PCI_CCNT_CCNT_DEFAULT 0x00000000u
#define PCI_CCNT_CCNT_OF(x) _VALUEOF(x)
#define PCI_CCNT_OF(x) _VALUEOF(x)
#define PCI_CCNT_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,CCNT,CCNT) \
)
#define PCI_CCNT_RMK(ccnt)\
(Uint32)( \
_PER_FMK(PCI,CCNT,CCNT,ccnt) \
)
#define _PCI_CCNT_FGET(FIELD)\
_PER_FGET(_PCI_CCNT_ADDR,PCI,CCNT,##FIELD)
/****************************************************************************\
* _____________________
* | |
* | H A L T |
* |___________________|
*
* HALT - PCI Transfer Halt Register
*
* FIELDS (msb -> lsb)
* (rw) HALT
*
\******************************************************************************/
#define _PCI_HALT_OFFSET 10
#if (C64_SUPPORT)
#define _PCI_HALT_ADDR 0x01C00028u
#else
#define _PCI_HALT_ADDR 0x01A40028u
#endif
#if (C64_SUPPORT)
#define _PCI_HALT_HALT_MASK 0x00000000u
#define _PCI_HALT_HALT_SHIFT 0x00000000u
#define PCI_HALT_HALT_DEFAULT 0x00000000u
#define PCI_HALT_HALT_OF(x) _VALUEOF(x)
#else
#define _PCI_HALT_HALT_MASK 0x00000001u
#define _PCI_HALT_HALT_SHIFT 0x00000000u
#define PCI_HALT_HALT_DEFAULT 0x00000000u
#define PCI_HALT_HALT_DEFAULT 0x00000000u
#define PCI_HALT_HALT_OF(x) _VALUEOF(x)
#define PCI_HALT_HALT_SET 0x00000001u
#endif
#define PCI_HALT_OF(x) _VALUEOF(x)
#define PCI_HALT_RMK(halt)\
(Uint32)( \
_PER_FMK(PCI,HALT,HALT,halt) \
)
#define PCI_HALT_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,HALT,HALT) \
)
#define _PCI_HALT_FGET(FIELD)\
_PER_FGET(_PCI_HALT_ADDR,PCI,HALT,##FIELD)
#define _PCI_HALT_FSET(FIELD,field)\
_PER_FSET(_PCI_HALT_ADDR,PCI,HALT,##FIELD,field)
#define _PCI_HALT_FSETS(FIELD,SYM)\
_PER_FSETS(_PCI_HALT_ADDR,PCI,HALT,##FIELD,##SYM)
/****************************************************************************\
* _____________________
* | |
* | E E A D D |
* |___________________|
*
* EEADD - EEPROM Address Register
*
* FIELDS (msb -> lsb)
* (rw) EEADD
*
\******************************************************************************/
#define _PCI_EEADD_OFFSET 0
#if (C64_SUPPORT)
#define _PCI_EEADD_ADDR 0x01C20000u
#else
#define _PCI_EEADD_ADDR 0x01A80000u
#endif
#define _PCI_EEADD_EEADD_MASK 0x000003FFu
#define _PCI_EEADD_EEADD_SHIFT 0x00000000u
#define PCI_EEADD_EEADD_DEFAULT 0x00000000u
#define PCI_EEADD_EEADD_OF(x) _VALUEOF(x)
#define PCI_EEADD_OF(x) _VALUEOF(x)
#define PCI_EEADD_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,EEADD,EEADD) \
)
#define PCI_EEADD_RMK(eeadd) \
(Uint32)( \
_PER_FMK(PCI,EEADD,EEADD,eeadd) \
)
#define _PCI_EEADD_FGET(FIELD)\
_PER_FGET(_PCI_EEADD_ADDR,PCI,EEADD,##FIELD)
#define _PCI_EEADD_FSET(FIELD,field)\
_PER_FSET(_PCI_EEADD_ADDR,PCI,EEADD,##FIELD,field)
#define _PCI_EEADD_FSETS(FIELD,SYM)\
_PER_FSETS(_PCI_EEADD_ADDR,PCI,EEADD,##FIELD,##SYM)
/****************************************************************************\
* _____________________
* | |
* | E E D A T |
* |___________________|
*
* EEDAT - EEPROM Data Register
*
* FIELDS (msb -> lsb)
* (rw) EEDAT
*
\*****************************************************************************/
#define _PCI_EEDAT_OFFSET 1
#if (C64_SUPPORT)
#define _PCI_EEDAT_ADDR 0x01C20004u
#else
#define _PCI_EEDAT_ADDR 0x01A80004u
#endif
#define _PCI_EEDAT_EEDAT_MASK 0x0000FFFFu
#define _PCI_EEDAT_EEDAT_SHIFT 0x00000000u
#define PCI_EEDAT_EEDAT_DEFAULT 0x00000000u
#define PCI_EEDAT_EEDAT_OF(x) _VALUEOF(x)
#define PCI_EEDAT_OF(x) _VALUEOF(x)
#define PCI_EEDAT_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,EEDAT,EEDAT) \
)
#define PCI_EEDAT_RMK(eedat) \
(Uint32)( \
_PER_FMK(PCI,EEDAT,EEDAT,eedat) \
)
#define _PCI_EEDAT_FGET(FIELD)\
_PER_FGET(_PCI_EEDAT_ADDR,PCI,EEDAT,##FIELD)
#define _PCI_EEDAT_FSET(FIELD,field)\
_PER_FSET(_PCI_EEDAT_ADDR,PCI,EEDAT,##FIELD,field)
#define _PCI_EEDAT_FSETS(FIELD,SYM)\
_PER_FSETS(_PCI_EEDAT_ADDR,PCI,EEDAT,##FIELD,##SYM)
/****************************************************************************\
* _____________________
* | |
* | E E C T L |
* |___________________|
*
* EECTL - EEPROM Control Register
*
* FIELDS (msb -> lsb)
* (r) CFGDONE
* (r) CFGERR
* (r) EEAI
* (r) EESZ
* (r) READY
* (rw) EECNT
*
\******************************************************************************/
#define _PCI_EECTL_OFFSET 2
#if (C64_SUPPORT)
#define _PCI_EECTL_ADDR 0x01C20008u
#else
#define _PCI_EECTL_ADDR 0x01A80008u
#endif
#define _PCI_EECTL_CFGDONE_MASK 0x00000100u
#define _PCI_EECTL_CFGDONE_SHIFT 0x00000008u
#define PCI_EECTL_CFGDONE_DEFAULT 0x00000000u
#define PCI_EECTL_CFGDONE_OF(x) _VALUEOF(x)
#define _PCI_EECTL_CFGERR_MASK 0x00000080u
#define _PCI_EECTL_CFGERR_SHIFT 0x00000007u
#define PCI_EECTL_CFGERR_DEFAULT 0x00000000u
#define PCI_EECTL_CFGERR_OF(x) _VALUEOF(x)
#define _PCI_EECTL_EEAI_MASK 0x00000040u
#define _PCI_EECTL_EEAI_SHIFT 0x00000006u
#define PCI_EECTL_EEAI_DEFAULT 0x00000000u
#define PCI_EECTL_EEAI_OF(x) _VALUEOF(x)
#define _PCI_EECTL_EESZ_MASK 0x00000038u
#define _PCI_EECTL_EESZ_SHIFT 0x00000003u
#define PCI_EECTL_EESZ_DEFAULT 0x00000000u
#define PCI_EECTL_EESZ_OF(x) _VALUEOF(x)
#define _PCI_EECTL_READY_MASK 0x00000004u
#define _PCI_EECTL_READY_SHIFT 0x00000002u
#define PCI_EECTL_READY_DEFAULT 0x00000000u
#define PCI_EECTL_READY_OF(x) _VALUEOF(x)
#define _PCI_EECTL_EECNT_MASK 0x00000003u
#define _PCI_EECTL_EECNT_SHIFT 0x00000000u
#define PCI_EECTL_EECNT_DEFAULT 0x00000000u
#define PCI_EECTL_EECNT_OF(x) _VALUEOF(x)
#define PCI_EECTL_EECNT_EWEN 0x00000000u
#define PCI_EECTL_EECNT_ERAL 0x00000000u
#define PCI_EECTL_EECNT_WRAL 0x00000000u
#define PCI_EECTL_EECNT_EWDS 0x00000000u
#define PCI_EECTL_EECNT_WRITE 0x00000001u
#define PCI_EECTL_EECNT_READ 0x00000002u
#define PCI_EECTL_EECNT_ERASE 0x00000003u
#define PCI_EECTL_OF(x) _VALUEOF(x)
#define PCI_EECTL_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,EECTL,CFGDONE) \
|_PER_FDEFAULT(PCI,EECTL,CFGERR) \
|_PER_FDEFAULT(PCI,EECTL,EEAI) \
|_PER_FDEFAULT(PCI,EECTL,EESZ) \
|_PER_FDEFAULT(PCI,EECTL,READY) \
|_PER_FDEFAULT(PCI,EECTL,EECNT) \
)
#define PCI_EECTL_RMK(eecnt) \
(Uint32)( \
_PER_FMK(PCI,EECTL,EECNT,eecnt) \
)
#define _PCI_EECTL_FGET(FIELD)\
_PER_FGET(_PCI_EECTL_ADDR,PCI,EECTL,##FIELD)
#define _PCI_EECTL_FSET(FIELD,field)\
_PER_FSET(_PCI_EECTL_ADDR,PCI,EECTL,##FIELD,field)
#define _PCI_EECTL_FSETS(FIELD,SYM)\
_PER_FSETS(_PCI_EECTL_ADDR,PCI,EECTL,##FIELD,##SYM)
/****************************************************************************\
* _____________________
* | |
* | T R C T L |
* |___________________|
*
* TRCTL - TR Control Register
*
* FIELDS (msb -> lsb)
* (rw) TRSTALL
* (rw) PRI
* (rw) PALLOC
*
\*****************************************************************************/
#if (C64_SUPPORT)
#define _PCI_TRCTL_OFFSET 0
#define _PCI_TRCTL_ADDR 0x01C30000u
#define _PCI_TRCTL_TRSTALL_MASK 0x00000100u
#define _PCI_TRCTL_TRSTALL_SHIFT 0x00000008u
#define PCI_TRCTL_TRSTALL_DEFAULT 0x00000000u
#define PCI_TRCTL_TRSTALL_OF(x) _VALUEOF(x)
#define _PCI_TRCTL_PRI_MASK 0x00000030u
#define _PCI_TRCTL_PRI_SHIFT 0x00000004u
#define PCI_TRCTL_PRI_DEFAULT 0x00000002u
#define PCI_TRCTL_PRI_OF(x) _VALUEOF(x)
#define _PCI_TRCTL_PALLOC_MASK 0x0000000Fu
#define _PCI_TRCTL_PALLOC_SHIFT 0x00000000u
#define PCI_TRCTL_PALLOC_DEFAULT 0x00000004u
#define PCI_TRCTL_PALLOC_OF(x) _VALUEOF(x)
#define PCI_TRCTL_OF(x) _VALUEOF(x)
#define PCI_TRCTL_DEFAULT (Uint32)( \
_PER_FDEFAULT(PCI,TRCTL,TRSTALL) \
|_PER_FDEFAULT(PCI,TRCTL,PRI) \
|_PER_FDEFAULT(PCI,TRCTL,PALLOC) \
)
#define PCI_TRCTL_RMK(trstall,pri,palloc) \
(Uint32)( \
_PER_FMK(PCI,TRCTL,TRSTALL,trctl) \
|_PER_FMK(PCI,TRCTL,PRI,pri) \
|_PER_FMK(PCI,TRCTL,PALLOC,palloc) \
)
#define _PCI_TRCTL_FGET(FIELD)\
_PER_FGET(_PCI_TRCTL_ADDR,PCI,TRCTL,##FIELD)
#define _PCI_TRCTL_FSET(FIELD,field)\
_PER_FSET(_PCI_TRCTL_ADDR,PCI,TRCTL,##FIELD,field)
#define _PCI_TRCTL_FSETS(FIELD,SYM)\
_PER_FSETS(_PCI_TRCTL_ADDR,PCI,TRCTL,##FIELD,##SYM)
#endif
/******************************************************************************/
#endif /* PCI_SUPPORT */
#endif /* _CSL_PCIHAL_H_ */
/******************************************************************************\
* End of pcihal.h
\******************************************************************************/
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