📄 csl_chiphal.h
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_PER_FDEFAULT(CHIP,FADCR,L2RMODE)\
|_PER_FDEFAULT(CHIP,FADCR,L2UNDER)\
|_PER_FDEFAULT(CHIP,FADCR,L2INEX)\
|_PER_FDEFAULT(CHIP,FADCR,L2OVER)\
|_PER_FDEFAULT(CHIP,FADCR,L2INFO)\
|_PER_FDEFAULT(CHIP,FADCR,L2INVAL)\
|_PER_FDEFAULT(CHIP,FADCR,L2DEN2)\
|_PER_FDEFAULT(CHIP,FADCR,L2DEN1)\
|_PER_FDEFAULT(CHIP,FADCR,L2NAN2)\
|_PER_FDEFAULT(CHIP,FADCR,L2NAN1)\
|_PER_FDEFAULT(CHIP,FADCR,L1RMODE)\
|_PER_FDEFAULT(CHIP,FADCR,L1UNDER)\
|_PER_FDEFAULT(CHIP,FADCR,L1INEX)\
|_PER_FDEFAULT(CHIP,FADCR,L1OVER)\
|_PER_FDEFAULT(CHIP,FADCR,L1INFO)\
|_PER_FDEFAULT(CHIP,FADCR,L1INVAL)\
|_PER_FDEFAULT(CHIP,FADCR,L1DEN2)\
|_PER_FDEFAULT(CHIP,FADCR,L1DEN1)\
|_PER_FDEFAULT(CHIP,FADCR,L1NAN2)\
|_PER_FDEFAULT(CHIP,FADCR,L1NAN1)\
)
#define CHIP_FADCR_MK(l2rmode,l2under,l2index,l2over,l2info,l2inval,\
l2den2,l2den1,l2nan2,l2nan1,l1rmode,l1under,l1inex,l1over,l1info,\
l1inval,l1den2,l1den1,l1nan2,l1nan1) (Uint32)( \
_PER_FMK(CHIP,FADCR,L2RMODE,l2rmode)\
|_PER_FMK(CHIP,FADCR,L2UNDER,l2under)\
|_PER_FMK(CHIP,FADCR,L2INEX,l2inex)\
|_PER_FMK(CHIP,FADCR,L2OVER,l2over)\
|_PER_FMK(CHIP,FADCR,L2INFO,l2info)\
|_PER_FMK(CHIP,FADCR,L2INVAL,l2inval)\
|_PER_FMK(CHIP,FADCR,L2DEN2,l2den2)\
|_PER_FMK(CHIP,FADCR,L2DEN1,l2den1)\
|_PER_FMK(CHIP,FADCR,L2NAN2,l2nan2)\
|_PER_FMK(CHIP,FADCR,L2NAN1,l2nan1)\
|_PER_FMK(CHIP,FADCR,L1RMODE,l1rmode)\
|_PER_FMK(CHIP,FADCR,L1UNDER,l1under)\
|_PER_FMK(CHIP,FADCR,L1INEX,l1inex)\
|_PER_FMK(CHIP,FADCR,L1OVER,l1over)\
|_PER_FMK(CHIP,FADCR,L1INFO,l1info)\
|_PER_FMK(CHIP,FADCR,L1INVAL,l1inval)\
|_PER_FMK(CHIP,FADCR,L1DEN2,l1den2)\
|_PER_FMK(CHIP,FADCR,L1DEN1,l1den1)\
|_PER_FMK(CHIP,FADCR,L1NAN2,l1nan2)\
|_PER_FMK(CHIP,FADCR,L1NAN1,l1nan1)\
)
#define _CHIP_FADCR_FGET(FIELD)\
_PER_CFGET(CHIP,FADCR,##FIELD)
#define _CHIP_FADCR_FSET(FIELD,field)\
_PER_CFSET(CHIP,FADCR,##FIELD,field)
#define _CHIP_FADCR_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,FADCR,##FIELD,##SYM)
#endif
/******************************************************************************\
* _____________________
* | |
* | F A U C R |
* |___________________|
*
* FAUCR - floating-point auxiliary config register (1)
*
* FIELDS (msb -> lsb)
* (rw) S2DIV0
* (rw) S2UNORD
* (rw) S2UND
* (rw) S2INEX
* (rw) S2OVER
* (rw) S2INFO
* (rw) S2INVAL
* (rw) S2DEN2
* (rw) S2DEN1
* (rw) S2NAN2
* (rw) S2NAN1
* (rw) S1DIV0
* (rw) S1UNORD
* (rw) S1UND
* (rw) S1INEX
* (rw) S1OVER
* (rw) S1INFO
* (rw) S1INVAL
* (rw) S1DEN2
* (rw) S1DEN1
* (rw) S1NAN2
* (rw) S1NAN1
*
* (1) only supported on devices with floating point unit
*
\******************************************************************************/
#if (FPU_SUPPORT)
extern far cregister volatile unsigned int FAUCR;
#define _CHIP_FAUCR_S2DIV0_MASK 0x04000000u
#define _CHIP_FAUCR_S2DIV0_SHIFT 0x0000001Au
#define CHIP_FAUCR_S2DIV0_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2DIV0_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2UNORD_MASK 0x02000000u
#define _CHIP_FAUCR_S2UNORD_SHIFT 0x00000019u
#define CHIP_FAUCR_S2UNORD_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2UNORD_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2UND_MASK 0x01000000u
#define _CHIP_FAUCR_S2UND_SHIFT 0x00000018u
#define CHIP_FAUCR_S2UND_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2UND_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2INEX_MASK 0x00800000u
#define _CHIP_FAUCR_S2INEX_SHIFT 0x00000017u
#define CHIP_FAUCR_S2INEX_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2INEX_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2OVER_MASK 0x00400000u
#define _CHIP_FAUCR_S2OVER_SHIFT 0x00000016u
#define CHIP_FAUCR_S2OVER_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2OVER_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2INFO_MASK 0x00200000u
#define _CHIP_FAUCR_S2INFO_SHIFT 0x00000015u
#define CHIP_FAUCR_S2INFO_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2INFO_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2INVAL_MASK 0x00100000u
#define _CHIP_FAUCR_S2INVAL_SHIFT 0x00000014u
#define CHIP_FAUCR_S2INVAL_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2INVAL_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2DEN2_MASK 0x00080000u
#define _CHIP_FAUCR_S2DEN2_SHIFT 0x00000013u
#define CHIP_FAUCR_S2DEN2_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2DEN2_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2DEN1_MASK 0x00040000u
#define _CHIP_FAUCR_S2DEN1_SHIFT 0x00000012u
#define CHIP_FAUCR_S2DEN1_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2DEN1_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2NAN2_MASK 0x00020000u
#define _CHIP_FAUCR_S2NAN2_SHIFT 0x00000011u
#define CHIP_FAUCR_S2NAN2_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2NAN2_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S2NAN1_MASK 0x00010000u
#define _CHIP_FAUCR_S2NAN1_SHIFT 0x00000010u
#define CHIP_FAUCR_S2NAN1_DEFAULT 0x00000000u
#define CHIP_FAUCR_S2NAN1_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1DIV0_MASK 0x00000400u
#define _CHIP_FAUCR_S1DIV0_SHIFT 0x0000000Au
#define CHIP_FAUCR_S1DIV0_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1DIV0_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1UNORD_MASK 0x00000200u
#define _CHIP_FAUCR_S1UNORD_SHIFT 0x00000009u
#define CHIP_FAUCR_S1UNORD_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1UNORD_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1UND_MASK 0x00000100u
#define _CHIP_FAUCR_S1UND_SHIFT 0x00000008u
#define CHIP_FAUCR_S1UND_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1UND_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1INEX_MASK 0x00000080u
#define _CHIP_FAUCR_S1INEX_SHIFT 0x00000007u
#define CHIP_FAUCR_S1INEX_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1INEX_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1OVER_MASK 0x00000040u
#define _CHIP_FAUCR_S1OVER_SHIFT 0x00000006u
#define CHIP_FAUCR_S1OVER_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1OVER_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1INFO_MASK 0x00000020u
#define _CHIP_FAUCR_S1INFO_SHIFT 0x00000005u
#define CHIP_FAUCR_S1INFO_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1INFO_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1INVAL_MASK 0x00000010u
#define _CHIP_FAUCR_S1INVAL_SHIFT 0x00000004u
#define CHIP_FAUCR_S1INVAL_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1INVAL_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1DEN2_MASK 0x00000008u
#define _CHIP_FAUCR_S1DEN2_SHIFT 0x00000003u
#define CHIP_FAUCR_S1DEN2_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1DEN2_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1DEN1_MASK 0x00000004u
#define _CHIP_FAUCR_S1DEN1_SHIFT 0x00000002u
#define CHIP_FAUCR_S1DEN1_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1DEN1_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1NAN2_MASK 0x00000002u
#define _CHIP_FAUCR_S1NAN2_SHIFT 0x00000001u
#define CHIP_FAUCR_S1NAN2_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1NAN2_OF(x) _VALUEOF(x)
#define _CHIP_FAUCR_S1NAN1_MASK 0x00000001u
#define _CHIP_FAUCR_S1NAN1_SHIFT 0x00000000u
#define CHIP_FAUCR_S1NAN1_DEFAULT 0x00000000u
#define CHIP_FAUCR_S1NAN1_OF(x) _VALUEOF(x)
#define CHIP_FAUCR_OF(x) _VALUEOF(x)
#define CHIP_FAUCR_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,FAUCR,S2DIV0)\
|_PER_FDEFAULT(CHIP,FAUCR,S2UNORD)\
|_PER_FDEFAULT(CHIP,FAUCR,S2UND)\
|_PER_FDEFAULT(CHIP,FAUCR,S2INEX)\
|_PER_FDEFAULT(CHIP,FAUCR,S2OVER)\
|_PER_FDEFAULT(CHIP,FAUCR,S2INFO)\
|_PER_FDEFAULT(CHIP,FAUCR,S2INVAL)\
|_PER_FDEFAULT(CHIP,FAUCR,S2DEN2)\
|_PER_FDEFAULT(CHIP,FAUCR,S2DEN1)\
|_PER_FDEFAULT(CHIP,FAUCR,S2NAN2)\
|_PER_FDEFAULT(CHIP,FAUCR,S2NAN1)\
|_PER_FDEFAULT(CHIP,FAUCR,S1DIV0)\
|_PER_FDEFAULT(CHIP,FAUCR,S1UNORD)\
|_PER_FDEFAULT(CHIP,FAUCR,S1UND)\
|_PER_FDEFAULT(CHIP,FAUCR,S1INEX)\
|_PER_FDEFAULT(CHIP,FAUCR,S1OVER)\
|_PER_FDEFAULT(CHIP,FAUCR,S1INFO)\
|_PER_FDEFAULT(CHIP,FAUCR,S1INVAL)\
|_PER_FDEFAULT(CHIP,FAUCR,S1DEN2)\
|_PER_FDEFAULT(CHIP,FAUCR,S1DEN1)\
|_PER_FDEFAULT(CHIP,FAUCR,S1NAN2)\
|_PER_FDEFAULT(CHIP,FAUCR,S1NAN1)\
)
#define CHIP_FAUCR_MK(s2div0,s2unord,s2und,s2inex,s2over,s2info,s2inval,\
s2den2,s2den1,s2nan2,s2nan1,s1div0,s1unord,s1und,s1inex,s1over,s1info,\
s1inval,s1den2,s1den1,s1nan2,s1nan1) (Uint32)( \
_PER_FMK(CHIP,FAUCR,S2DIV0,s2div)\
|_PER_FMK(CHIP,FAUCR,S2UNORD,s2unord)\
|_PER_FMK(CHIP,FAUCR,S2UND,s2und)\
|_PER_FMK(CHIP,FAUCR,S2INEX,s2inex)\
|_PER_FMK(CHIP,FAUCR,S2OVER,s2over)\
|_PER_FMK(CHIP,FAUCR,S2INFO,s2info)\
|_PER_FMK(CHIP,FAUCR,S2INVAL,s2inval)\
|_PER_FMK(CHIP,FAUCR,S2DEN2,s2den2)\
|_PER_FMK(CHIP,FAUCR,S2DEN1,s2den1)\
|_PER_FMK(CHIP,FAUCR,S2NAN2,s2nan2)\
|_PER_FMK(CHIP,FAUCR,S2NAN1,s2nan1)\
|_PER_FMK(CHIP,FAUCR,S1DIV0,s1div0)\
|_PER_FMK(CHIP,FAUCR,S1UNORD,s1unord)\
|_PER_FMK(CHIP,FAUCR,S1UND,s1und)\
|_PER_FMK(CHIP,FAUCR,S1INEX,s1inex)\
|_PER_FMK(CHIP,FAUCR,S1OVER,s1over)\
|_PER_FMK(CHIP,FAUCR,S1INFO,s1info)\
|_PER_FMK(CHIP,FAUCR,S1INVAL,s1inval)\
|_PER_FMK(CHIP,FAUCR,S1DEN2,s1den2)\
|_PER_FMK(CHIP,FAUCR,S1DEN1,s1den1)\
|_PER_FMK(CHIP,FAUCR,S1NAN2,s1nan2)\
|_PER_FMK(CHIP,FAUCR,S1NAN1,s1nan1)\
)
#define _CHIP_FAUCR_FGET(FIELD)\
_PER_CFGET(CHIP,FAUCR,##FIELD)
#define _CHIP_FAUCR_FSET(FIELD,field)\
_PER_CFSET(CHIP,FAUCR,##FIELD,field)
#define _CHIP_FAUCR_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,FAUCR,##FIELD,##SYM)
#endif
/******************************************************************************\
* _____________________
* | |
* | F M C R |
* |___________________|
*
* FMCR - floating-point multiplier config register (1)
*
* FIELDS (msb -> lsb)
* (rw) M2RMODE
* (rw) M2UNDER
* (rw) M2INEX
* (rw) M2OVER
* (rw) M2INFO
* (rw) M2INVAL
* (rw) M2DEN2
* (rw) M2DEN1
* (rw) M2NAN2
* (rw) M2NAN1
* (rw) M1RMODE
* (rw) M1UNDER
* (rw) M1INEX
* (rw) M1OVER
* (rw) M1INFO
* (rw) M1INVAL
* (rw) M1DEN2
* (rw) M1DEN1
* (rw) M1NAN2
* (rw) M1NAN1
*
* (1) only supported on devices with floating point unit
*
\******************************************************************************/
#if (FPU_SUPPORT)
extern far cregister volatile unsigned int FMCR;
#define _CHIP_FMCR_M2RMODE_MASK 0x06000000u
#define _CHIP_FMCR_M2RMODE_SHIFT 0x00000019u
#define CHIP_FMCR_M2RMODE_DEFAULT 0x00000000u
#define CHIP_FMCR_M2RMODE_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2UNDER_MASK 0x01000000u
#define _CHIP_FMCR_M2UNDER_SHIFT 0x00000018u
#define CHIP_FMCR_M2UNDER_DEFAULT 0x00000000u
#define CHIP_FMCR_M2UNDER_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2INEX_MASK 0x00800000u
#define _CHIP_FMCR_M2INEX_SHIFT 0x00000017u
#define CHIP_FMCR_M2INEX_DEFAULT 0x00000000u
#define CHIP_FMCR_M2INEX_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2OVER_MASK 0x00400000u
#define _CHIP_FMCR_M2OVER_SHIFT 0x00000016u
#define CHIP_FMCR_M2OVER_DEFAULT 0x00000000u
#define CHIP_FMCR_M2OVER_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2INFO_MASK 0x00200000u
#define _CHIP_FMCR_M2INFO_SHIFT 0x00000015u
#define CHIP_FMCR_M2INFO_DEFAULT 0x00000000u
#define CHIP_FMCR_M2INFO_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2INVAL_MASK 0x00100000u
#define _CHIP_FMCR_M2INVAL_SHIFT 0x00000014u
#define CHIP_FMCR_M2INVAL_DEFAULT 0x00000000u
#define CHIP_FMCR_M2INVAL_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2DEN2_MASK 0x00080000u
#define _CHIP_FMCR_M2DEN2_SHIFT 0x00000013u
#define CHIP_FMCR_M2DEN2_DEFAULT 0x00000000u
#define CHIP_FMCR_M2DEN2_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2DEN1_MASK 0x00040000u
#define _CHIP_FMCR_M2DEN1_SHIFT 0x00000012u
#define CHIP_FMCR_M2DEN1_DEFAULT 0x00000000u
#define CHIP_FMCR_M2DEN1_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2NAN2_MASK 0x00020000u
#define _CHIP_FMCR_M2NAN2_SHIFT 0x00000011u
#define CHIP_FMCR_M2NAN2_DEFAULT 0x00000000u
#define CHIP_FMCR_M2NAN2_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M2NAN1_MASK 0x00010000u
#define _CHIP_FMCR_M2NAN1_SHIFT 0x00000010u
#define CHIP_FMCR_M2NAN1_DEFAULT 0x00000000u
#define CHIP_FMCR_M2NAN1_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M1RMODE_MASK 0x00000600u
#define _CHIP_FMCR_M1RMODE_SHIFT 0x00000009u
#define CHIP_FMCR_M1RMODE_DEFAULT 0x00000000u
#define CHIP_FMCR_M1RMODE_OF(x) _VALUEOF(x)
#define _CHIP_FMCR_M1UNDER_MASK 0x00000100u
#define _CHIP_FMCR_M1UNDER_SHIFT 0x00000008u
#define CHIP_FMCR_M1UNDER_DEFAULT 0x00000000u
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