📄 csl_chiphal.h
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#define CHIP_CSR_CPUID_DEFAULT 0x00000000u
#define CHIP_CSR_CPUID_OF(x) _VALUEOF(x)
#define CHIP_CSR_CPUID_C62X 0x00000000u
#define CHIP_CSR_CPUID_C67X 0x00000002u
#define CHIP_CSR_CPUID_C64X 0x00000004u
#define _CHIP_CSR_REVID_MASK 0x00FF0000u
#define _CHIP_CSR_REVID_SHIFT 0x00000010u
#define CHIP_CSR_REVID_DEFAULT 0x00000000u
#define CHIP_CSR_REVID_OF(x) _VALUEOF(x)
#define CHIP_CSR_REVID_620120 0x00000001u
#define CHIP_CSR_REVID_620121 0x00000001u
#define CHIP_CSR_REVID_620130 0x00000002u
#define CHIP_CSR_REVID_670100 0x00000201u
#define CHIP_CSR_REVID_670110 0x00000202u
#define CHIP_CSR_REVID_621110 0x00000002u
#define CHIP_CSR_REVID_640010 0x00000801u
#define CHIP_CSR_REVID_6202 0x00000002u
#define CHIP_CSR_REVID_6202B 0x00000003u
#define CHIP_CSR_REVID_6711 0x00000002u
#define CHIP_CSR_REVID_6711C 0x00000003u
#define CHIP_CSR_REVID_6712 0x00000002u
#define CHIP_CSR_REVID_6712C 0x00000003u
#define _CHIP_CSR_PWRD_MASK 0x0000FC00u
#define _CHIP_CSR_PWRD_SHIFT 0x0000000Au
#define CHIP_CSR_PWRD_DEFAULT 0x00000000u
#define CHIP_CSR_PWRD_OF(x) _VALUEOF(x)
#define CHIP_CSR_PWRD_NONE 0x00000000u
#define CHIP_CSR_PWRD_PD1A 0x00000009u
#define CHIP_CSR_PWRD_PD1B 0x00000011u
#define CHIP_CSR_PWRD_PD2 0x0000001Au
#define CHIP_CSR_PWRD_PD3 0x0000001Cu
#define _CHIP_CSR_SAT_MASK 0x00000200u
#define _CHIP_CSR_SAT_SHIFT 0x00000009u
#define CHIP_CSR_SAT_DEFAULT 0x00000000u
#define CHIP_CSR_SAT_OF(x) _VALUEOF(x)
#define CHIP_CSR_SAT_0 0x00000000u
#define CHIP_CSR_SAT_1 0x00000001u
#define _CHIP_CSR_EN_MASK 0x00000100u
#define _CHIP_CSR_EN_SHIFT 0x00000008u
#define CHIP_CSR_EN_DEFAULT 0x00000000u
#define CHIP_CSR_EN_OF(x) _VALUEOF(x)
#define CHIP_CSR_EN_BIG 0x00000000u
#define CHIP_CSR_EN_LITTLE 0x00000001u
#define _CHIP_CSR_PCC_MASK 0x000000E0u
#define _CHIP_CSR_PCC_SHIFT 0x00000005u
#define CHIP_CSR_PCC_DEFAULT 0x00000000u
#define CHIP_CSR_PCC_OF(x) _VALUEOF(x)
#define CHIP_CSR_PCC_MAPPED 0x00000000u
#define CHIP_CSR_PCC_ENABLE 0x00000002u
#define CHIP_CSR_PCC_FREEZE 0x00000003u
#define CHIP_CSR_PCC_BYPASS 0x00000004u
#define _CHIP_CSR_DCC_MASK 0x0000001Cu
#define _CHIP_CSR_DCC_SHIFT 0x00000002u
#define CHIP_CSR_DCC_DEFAULT 0x00000000u
#define CHIP_CSR_DCC_OF(x) _VALUEOF(x)
#define CHIP_CSR_DCC_MAPPED 0x00000000u
#define CHIP_CSR_DCC_ENABLE 0x00000002u
#define CHIP_CSR_DCC_FREEZE 0x00000003u
#define CHIP_CSR_DCC_BYPASS 0x00000004u
#define _CHIP_CSR_PGIE_MASK 0x00000002u
#define _CHIP_CSR_PGIE_SHIFT 0x00000001u
#define CHIP_CSR_PGIE_DEFAULT 0x00000000u
#define CHIP_CSR_PGIE_OF(x) _VALUEOF(x)
#define CHIP_CSR_PGIE_0 0x00000000u
#define CHIP_CSR_PGIE_1 0x00000001u
#define _CHIP_CSR_GIE_MASK 0x00000001u
#define _CHIP_CSR_GIE_SHIFT 0x00000000u
#define CHIP_CSR_GIE_DEFAULT 0x00000000u
#define CHIP_CSR_GIE_OF(x) _VALUEOF(x)
#define CHIP_CSR_GIE_0 0x00000000u
#define CHIP_CSR_GIE_1 0x00000001u
#define CHIP_CSR_OF(x) _VALUEOF(x)
#define CHIP_CSR_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,CSR,CPUID) \
|_PER_FDEFAULT(CHIP,CSR,REVID) \
|_PER_FDEFAULT(CHIP,CSR,PWRD) \
|_PER_FDEFAULT(CHIP,CSR,SAT) \
|_PER_FDEFAULT(CHIP,CSR,EN) \
|_PER_FDEFAULT(CHIP,CSR,PCC) \
|_PER_FDEFAULT(CHIP,CSR,DCC) \
|_PER_FDEFAULT(CHIP,CSR,PGIE) \
|_PER_FDEFAULT(CHIP,CSR,GIE) \
)
#define CHIP_CSR_RMK(pwrd,pcc,dcc,pgie,gie) (Uint32)( \
_PER_FMK(CHIP,CSR,PWRD,pwrd) \
|_PER_FMK(CHIP,CSR,PCC,pcc) \
|_PER_FMK(CHIP,CSR,DCC,dcc) \
|_PER_FMK(CHIP,CSR,PGIE,pgie) \
|_PER_FMK(CHIP,CSR,GIE,gie) \
)
#define _CHIP_CSR_FGET(FIELD)\
_PER_CFGET(CHIP,CSR,##FIELD)
#define _CHIP_CSR_FSET(FIELD,field)\
_PER_CFSET(CHIP,CSR,##FIELD,field)
#define _CHIP_CSR_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,CSR,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | I F R |
* |___________________|
*
* IFR - interruppt flag register
*
* FIELDS (msb -> lsb)
* (rw) IF
*
\******************************************************************************/
extern far cregister volatile unsigned int IFR;
#define _CHIP_IFR_IF_MASK 0x0000FFFFu
#define _CHIP_IFR_IF_SHIFT 0x00000000u
#define CHIP_IFR_IF_DEFAULT 0x00000000u
#define CHIP_IFR_IF_OF(x) _VALUEOF(x)
#define CHIP_IFR_OF(x) _VALUEOF(x)
#define CHIP_IFR_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,IFR,IF)\
)
#define CHIP_IFR_RMK(if) (Uint32)( \
_PER_FMK(CHIP,IFR,IF,if)\
)
#define _CHIP_IFR_FGET(FIELD)\
_PER_CFGET(CHIP,IFR,##FIELD)
#define _CHIP_IFR_FSET(FIELD,field)\
_PER_CFSET(CHIP,IFR,##FIELD,field)
#define _CHIP_IFR_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,IFR,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | I S R |
* |___________________|
*
* ISR - interruppt set register
*
* FIELDS (msb -> lsb)
* (w) IS
*
\******************************************************************************/
extern far cregister volatile unsigned int ISR;
#define _CHIP_ISR_IS_MASK 0x0000FFFFu
#define _CHIP_ISR_IS_SHIFT 0x00000000u
#define CHIP_ISR_IS_DEFAULT 0x00000000u
#define CHIP_ISR_IS_OF(x) _VALUEOF(x)
#define CHIP_ISR_OF(x) _VALUEOF(x)
#define CHIP_ISR_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,ISR,IS)\
)
#define CHIP_ISR_RMK(is) (Uint32)( \
_PER_FMK(CHIP,ISR,IS,is)\
)
#define _CHIP_ISR_FGET(FIELD)\
_PER_CFGET(CHIP,ISR,##FIELD)
#define _CHIP_ISR_FSET(FIELD,field)\
_PER_CFSET(CHIP,ISR,##FIELD,field)
#define _CHIP_ISR_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,ISR,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | I C R |
* |___________________|
*
* ICR - interruppt clear register
*
* FIELDS (msb -> lsb)
* (w) IC
*
\******************************************************************************/
extern far cregister volatile unsigned int ICR;
#define _CHIP_ICR_IC_MASK 0x0000FFFFu
#define _CHIP_ICR_IC_SHIFT 0x00000000u
#define CHIP_ICR_IC_DEFAULT 0x00000000u
#define CHIP_ICR_IC_OF(x) _VALUEOF(x)
#define CHIP_ICR_OF(x) _VALUEOF(x)
#define CHIP_ICR_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,ICR,IC)\
)
#define CHIP_ICR_RMK(ic) (Uint32)( \
_PER_FMK(CHIP,ICR,IC,ic)\
)
#define _CHIP_ICR_FGET(FIELD)\
_PER_CFGET(CHIP,ICR,##FIELD)
#define _CHIP_ICR_FSET(FIELD,field)\
_PER_CFSET(CHIP,ICR,##FIELD,field)
#define _CHIP_ICR_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,ICR,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | I E R |
* |___________________|
*
* IER - interruppt enable register
*
* FIELDS (msb -> lsb)
* (rw) IE
*
\******************************************************************************/
extern far cregister volatile unsigned int IER;
#define _CHIP_IER_IE_MASK 0x0000FFFFu
#define _CHIP_IER_IE_SHIFT 0x00000000u
#define CHIP_IER_IE_DEFAULT 0x00000000u
#define CHIP_IER_IE_OF(x) _VALUEOF(x)
#define CHIP_IER_OF(x) _VALUEOF(x)
#define CHIP_IER_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,IER,IE)\
)
#define CHIP_IER_RMK(ie) (Uint32)( \
_PER_FMK(CHIP,IER,IE,ie)\
)
#define _CHIP_IER_FGET(FIELD)\
_PER_CFGET(CHIP,IER,##FIELD)
#define _CHIP_IER_FSET(FIELD,field)\
_PER_CFSET(CHIP,IER,##FIELD,field)
#define _CHIP_IER_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,IER,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | I S T P |
* |___________________|
*
* ISTP - interrupt service table pointer
*
* FIELDS (msb -> lsb)
* (r) HPEINT
* (rw) ISTB
*
\******************************************************************************/
extern far cregister volatile unsigned int ISTP;
#define _CHIP_ISTP_ISTB_MASK 0xFFFFFC00u
#define _CHIP_ISTP_ISTB_SHIFT 0x0000000Au
#define CHIP_ISTP_ISTB_DEFAULT 0x00000000u
#define CHIP_ISTP_ISTB_OF(x) _VALUEOF(x)
#define _CHIP_ISTP_HPEINT_MASK 0x000003E0u
#define _CHIP_ISTP_HPEINT_SHIFT 0x00000005u
#define CHIP_ISTP_HPEINT_DEFAULT 0x00000000u
#define CHIP_ISTP_HPEINT_OF(x) _VALUEOF(x)
#define CHIP_ISTP_OF(x) _VALUEOF(x)
#define CHIP_ISTP_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,ISTP,ISTB)\
|_PER_FDEFAULT(CHIP,ISTP,HPEINT)\
)
#define CHIP_ISTP_RMK(istb) (Uint32)( \
_PER_FMK(CHIP,ISTP,ISTB,istb)\
)
#define _CHIP_ISTP_FGET(FIELD)\
_PER_CFGET(CHIP,ISTP,##FIELD)
#define _CHIP_ISTP_FSET(FIELD,field)\
_PER_CFSET(CHIP,ISTP,##FIELD,field)
#define _CHIP_ISTP_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,ISTP,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | I R P |
* |___________________|
*
* IRP - interrupt return pointer
*
* FIELDS (msb -> lsb)
* (rw) IRP
*
\******************************************************************************/
extern far cregister volatile unsigned int IRP;
#define _CHIP_IRP_IRP_MASK 0xFFFFFFFFu
#define _CHIP_IRP_IRP_SHIFT 0x00000000u
#define CHIP_IRP_IRP_DEFAULT 0x00000000u
#define CHIP_IRP_IRP_OF(x) _VALUEOF(x)
#define CHIP_IRP_OF(x) _VALUEOF(x)
#define CHIP_IRP_DEFAULT (Uint32)( \
_PER_FDEFAULT(CHIP,IRP,IRP)\
)
#define CHIP_IRP_RMK(irp) (Uint32)( \
_PER_FMK(CHIP,IRP,IRP,irp)\
)
#define _CHIP_IRP_FGET(FIELD)\
_PER_CFGET(CHIP,IRP,##FIELD)
#define _CHIP_IRP_FSET(FIELD,field)\
_PER_CFSET(CHIP,IRP,##FIELD,field)
#define _CHIP_IRP_FSETS(FIELD,SYM)\
_PER_CFSETS(CHIP,IRP,##FIELD,##SYM)
/******************************************************************************\
* _____________________
* | |
* | N R P |
* |___________________|
*
* NRP - non-maskable interrupt return pointer
*
* FIELDS (msb -> lsb)
* (rw) NRP
*
\******************************************************************************/
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