📄 c64.h64
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;
; Copyright 2003 by Texas Instruments Incorporated.
; All rights reserved. Property of Texas Instruments Incorporated.
; Restricted rights to use, duplicate or disclose this code are
; granted through contract.
;
;
; "@(#) DSP/BIOS 4.90.270 12-18-03 (barracuda-o04)"
;
; ======== c64.h64 ========
; Assembly language c64 macros
;
; instead of 1 due to 5-bit offset limit.
;
.if ($isdefed("C64_") = 0) ; prevent multiple includes
C64_ .set 1
;
; Symbol and constant definitions
;
.asg a15, FP ; Frame Pointer
.asg b14, DP ; Data Page Register
.asg b15, SP ; Stack Pointer
GIE .set 0x0001 ; Global Interrupt Enable bit in CSR
SAT .set 0x0200 ; SAT bit in CSR
;
; Values used for CCMASK in HWI_enter/HWI_exit.
;
C64_PCC_DISABLE .set 0x0000 ; Program Cache Control code
C64_PCC_ENABLE .set 0x0040 ; Program Cache Control code
C64_PCC_FREEZE .set 0x0060 ; Program Cache Control code
C64_PCC_BYPASS .set 0x0080 ; Program Cache Control code
C64_CCFIELDS .set 0x00fc ; Cache Control field mask
;
; Register bitmap position definitions used below
;
C64_ra0 .set 0
C64_ra1 .set 1
C64_ra2 .set 2
C64_ra3 .set 3
C64_ra4 .set 4
C64_ra5 .set 5
C64_ra6 .set 6
C64_ra7 .set 7
C64_ra8 .set 8
C64_ra9 .set 9
C64_ra10 .set 10
C64_ra11 .set 11
C64_ra12 .set 12
C64_ra13 .set 13
C64_ra14 .set 14
C64_ra15 .set 15
C64_ra16 .set 16
C64_ra17 .set 17
C64_ra18 .set 18
C64_ra19 .set 19
C64_ra20 .set 20
C64_ra21 .set 21
C64_ra22 .set 22
C64_ra23 .set 23
C64_ra24 .set 24
C64_ra25 .set 25
C64_ra26 .set 26
C64_ra27 .set 27
C64_ra28 .set 28
C64_ra29 .set 29
C64_ra30 .set 30
C64_ra31 .set 31
C64_rb0 .set 0
C64_rb1 .set 1
C64_rb2 .set 2
C64_rb3 .set 3
C64_rb4 .set 4
C64_rb5 .set 5
C64_rb6 .set 6
C64_rb7 .set 7
C64_rb8 .set 8
C64_rb9 .set 9
C64_rb10 .set 10
C64_rb11 .set 11
C64_rb12 .set 12
C64_rb13 .set 13
C64_rb14 .set 14
C64_rb15 .set 15
C64_rb16 .set 16
C64_rb17 .set 17
C64_rb18 .set 18
C64_rb19 .set 19
C64_rb20 .set 20
C64_rb21 .set 21
C64_rb22 .set 22
C64_rb23 .set 23
C64_rb24 .set 24
C64_rb25 .set 25
C64_rb26 .set 26
C64_rb27 .set 27
C64_rb28 .set 28
C64_rb29 .set 29
C64_rb30 .set 30
C64_rb31 .set 31
C64_ramr .set 0
C64_rcsr .set 1
C64_rier .set 2
C64_rist .set 3
C64_rirp .set 4
C64_rnrp .set 5
;
; Definitions for C64_xTEMPS
;
C64_A0 .set 1 << C64_ra0
C64_A1 .set 1 << C64_ra1
C64_A2 .set 1 << C64_ra2
C64_A3 .set 1 << C64_ra3
C64_A4 .set 1 << C64_ra4
C64_A5 .set 1 << C64_ra5
C64_A6 .set 1 << C64_ra6
C64_A7 .set 1 << C64_ra7
C64_A8 .set 1 << C64_ra8
C64_A9 .set 1 << C64_ra9
C64_A10 .set 1 << C64_ra10
C64_A11 .set 1 << C64_ra11
C64_A12 .set 1 << C64_ra12
C64_A13 .set 1 << C64_ra13
C64_A14 .set 1 << C64_ra14
C64_A15 .set 1 << C64_ra15
C64_A16 .set 1 << C64_ra16
C64_A17 .set 1 << C64_ra17
C64_A18 .set 1 << C64_ra18
C64_A19 .set 1 << C64_ra19
C64_A20 .set 1 << C64_ra20
C64_A21 .set 1 << C64_ra21
C64_A22 .set 1 << C64_ra22
C64_A23 .set 1 << C64_ra23
C64_A24 .set 1 << C64_ra24
C64_A25 .set 1 << C64_ra25
C64_A26 .set 1 << C64_ra26
C64_A27 .set 1 << C64_ra27
C64_A28 .set 1 << C64_ra28
C64_A29 .set 1 << C64_ra29
C64_A30 .set 1 << C64_ra30
C64_A31 .set 1 << C64_ra31
C64_B0 .set 1 << C64_rb0
C64_B1 .set 1 << C64_rb1
C64_B2 .set 1 << C64_rb2
C64_B3 .set 1 << C64_rb3
C64_B4 .set 1 << C64_rb4
C64_B5 .set 1 << C64_rb5
C64_B6 .set 1 << C64_rb6
C64_B7 .set 1 << C64_rb7
C64_B8 .set 1 << C64_rb8
C64_B9 .set 1 << C64_rb9
C64_B10 .set 1 << C64_rb10
C64_B11 .set 1 << C64_rb11
C64_B12 .set 1 << C64_rb12
C64_B13 .set 1 << C64_rb13
C64_B14 .set 1 << C64_rb14
C64_B15 .set 1 << C64_rb15
C64_B16 .set 1 << C64_rb16
C64_B17 .set 1 << C64_rb17
C64_B18 .set 1 << C64_rb18
C64_B19 .set 1 << C64_rb19
C64_B20 .set 1 << C64_rb20
C64_B21 .set 1 << C64_rb21
C64_B22 .set 1 << C64_rb22
C64_B23 .set 1 << C64_rb23
C64_B24 .set 1 << C64_rb24
C64_B25 .set 1 << C64_rb25
C64_B26 .set 1 << C64_rb26
C64_B27 .set 1 << C64_rb27
C64_B28 .set 1 << C64_rb28
C64_B29 .set 1 << C64_rb29
C64_B30 .set 1 << C64_rb30
C64_B31 .set 1 << C64_rb31
C64_AMR .set 1 << C64_ramr ; Addressing mode register
C64_CSR .set 1 << C64_rcsr ; Control status register
C64_IER .set 1 << C64_rier ; Interrupt enable register
C64_IST .set 1 << C64_rist ; Interrupt service table pointer
C64_IRP .set 1 << C64_rirp ; Interrupt return pointer
C64_NRP .set 1 << C64_rnrp ; Non-maskable int. return pointer
;
; Interrupt Enable Register (and Interrupt Flag Register) bit definitions
;
C64_NMIE .set 1 << 1 ; Non-maskable Interrupt Enable bit
C64_IE2 .set 1 << 2 ; Reserved Interrupt 2 Enable
C64_IE3 .set 1 << 3 ; Reserved Interrupt 3 Enable
C64_IE4 .set 1 << 4 ; Interrupt Enable 4
C64_IE5 .set 1 << 5 ; Interrupt Enable 5
C64_IE6 .set 1 << 6 ; Interrupt Enable 6
C64_IE7 .set 1 << 7 ; Interrupt Enable 7
C64_IE8 .set 1 << 8 ; Interrupt Enable 8
C64_IE9 .set 1 << 9 ; Interrupt Enable 9
C64_IE10 .set 1 << 10 ; Interrupt Enable 10
C64_IE11 .set 1 << 11 ; Interrupt Enable 11
C64_IE12 .set 1 << 12 ; Interrupt Enable 12
C64_IE13 .set 1 << 13 ; Interrupt Enable 13
C64_IE14 .set 1 << 14 ; Interrupt Enable 14
C64_IE15 .set 1 << 15 ; Interrupt Enable 15
;
; Masks for ISR registers saved and restored internally
;
C64_ISRA .set C64_A0 | C64_A1 | C64_A2 | C64_A3
C64_ISRB .set C64_B0 | C64_B1 | C64_B2 | C64_B3 | C64_B14
C64_ISRC .set C64_AMR | C64_IRP | C64_IER
;
; Register combinations
;
C64_ATEMPSLO .set C64_A0 | C64_A1 | C64_A2 | C64_A3 | C64_A4
C64_ATEMPSHI .set C64_A5 | C64_A6 | C64_A7 | C64_A8 | C64_A9
C64_ATEMPSUP1 .set C64_A16 | C64_A17 | C64_A18 | C64_A19 | C64_A20
C64_ATEMPSUP2 .set C64_A21 | C64_A22 | C64_A23 | C64_A24 | C64_A25
C64_ATEMPSUP3 .set C64_A26 | C64_A27 | C64_A28 | C64_A29 | C64_A30 |C64_A31
C64_ATEMPSUP .set C64_ATEMPSUP1 | C64_ATEMPSUP2 | C64_ATEMPSUP3
C64_ATEMPS .set C64_ATEMPSLO | C64_ATEMPSHI | C64_ATEMPSUP
C64_BTEMPSLO .set C64_B0 | C64_B1 | C64_B2 | C64_B3 | C64_B4
C64_BTEMPSHI .set C64_B5 | C64_B6 | C64_B7 | C64_B8 | C64_B9
C64_BTEMPSUP1 .set C64_B16 | C64_B17 | C64_B18 | C64_B19 | C64_B20
C64_BTEMPSUP2 .set C64_B21 | C64_B22 | C64_B23 | C64_B24 | C64_B25
C64_BTEMPSUP3 .set C64_B26 | C64_B27 | C64_B28 | C64_B29 | C64_B30 |C64_B31
C64_BTEMPSUP .set C64_BTEMPSUP1 | C64_BTEMPSUP2 | C64_BTEMPSUP3
C64_BTEMPS .set C64_BTEMPSLO | C64_BTEMPSHI | C64_BTEMPSUP
C64_CTEMPS .set C64_AMR
;
;# ======== C64_set ========
;
; This macro conditionally sets bits in two masks corresponding to a passed
; list of registers. The first parameter is the name of the AB register
; mask, and the second is the name of the control register mask. This macro
; is typically used to prior to calls to C64_save and C64_restore.
;
; C64_set ABMASK, CMASK
;
; ABMASK - Mask of A and B registers included in the list
; CMASK - Mask of control registers included in the list
;#
;# Preconditions:
;# none
;#
;# Postconditions:
;# none
;#
;
.asg "", C64_set$regs
C64_set .macro ab_mask, c_mask, reglist
.var abmask,cmask,reg
.asg 0,abmask
.asg 0,cmask
.loop ; loop thru all regs in list
.break $ismember(reg,reglist) == 0 ; break when no more in list
.if $symcmp(reg,"a0") == 0 ; A registers
.eval abmask | C64_A0, abmask
.elseif $symcmp(reg,"A0") == 0
.eval abmask | C64_A0, abmask
.elseif $symcmp(reg,"a1") == 0
.eval abmask | C64_A1, abmask
.elseif $symcmp(reg,"A1") == 0
.eval abmask | C64_A1, abmask
.elseif $symcmp(reg,"a2") == 0
.eval abmask | C64_A2, abmask
.elseif $symcmp(reg,"A2") == 0
.eval abmask | C64_A2, abmask
.elseif $symcmp(reg,"a3") == 0
.eval abmask | C64_A3, abmask
.elseif $symcmp(reg,"A3") == 0
.eval abmask | C64_A3, abmask
.elseif $symcmp(reg,"a4") == 0
.eval abmask | C64_A4, abmask
.elseif $symcmp(reg,"A4") == 0
.eval abmask | C64_A4, abmask
.elseif $symcmp(reg,"a5") == 0
.eval abmask | C64_A5, abmask
.elseif $symcmp(reg,"A5") == 0
.eval abmask | C64_A5, abmask
.elseif $symcmp(reg,"a6") == 0
.eval abmask | C64_A6, abmask
.elseif $symcmp(reg,"A6") == 0
.eval abmask | C64_A6, abmask
.elseif $symcmp(reg,"a7") == 0
.eval abmask | C64_A7, abmask
.elseif $symcmp(reg,"A7") == 0
.eval abmask | C64_A7, abmask
.elseif $symcmp(reg,"a8") == 0
.eval abmask | C64_A8, abmask
.elseif $symcmp(reg,"A8") == 0
.eval abmask | C64_A8, abmask
.elseif $symcmp(reg,"a9") == 0
.eval abmask | C64_A9, abmask
.elseif $symcmp(reg,"A9") == 0
.eval abmask | C64_A9, abmask
.elseif $symcmp(reg,"a10") == 0
.eval abmask | C64_A10, abmask
.elseif $symcmp(reg,"A10") == 0
.eval abmask | C64_A10, abmask
.elseif $symcmp(reg,"a11") == 0
.eval abmask | C64_A11, abmask
.elseif $symcmp(reg,"A11") == 0
.eval abmask | C64_A11, abmask
.elseif $symcmp(reg,"a12") == 0
.eval abmask | C64_A12, abmask
.elseif $symcmp(reg,"A12") == 0
.eval abmask | C64_A12, abmask
.elseif $symcmp(reg,"a13") == 0
.eval abmask | C64_A13, abmask
.elseif $symcmp(reg,"A13") == 0
.eval abmask | C64_A13, abmask
.elseif $symcmp(reg,"a14") == 0
.eval abmask | C64_A14, abmask
.elseif $symcmp(reg,"A14") == 0
.eval abmask | C64_A14, abmask
.elseif $symcmp(reg,"a15") == 0
.eval abmask | C64_A15, abmask
.elseif $symcmp(reg,"A15") == 0
.eval abmask | C64_A15, abmask
.elseif $symcmp(reg,"b0") == 0 ; B registers
.eval abmask | C64_B0, abmask
.elseif $symcmp(reg,"B0") == 0
.eval abmask | C64_B0, abmask
.elseif $symcmp(reg,"b1") == 0
.eval abmask | C64_B1, abmask
.elseif $symcmp(reg,"B1") == 0
.eval abmask | C64_B1, abmask
.elseif $symcmp(reg,"b2") == 0
.eval abmask | C64_B2, abmask
.elseif $symcmp(reg,"B2") == 0
.eval abmask | C64_B2, abmask
.elseif $symcmp(reg,"b3") == 0
.eval abmask | C64_B3, abmask
.elseif $symcmp(reg,"B3") == 0
.eval abmask | C64_B3, abmask
.elseif $symcmp(reg,"b4") == 0
.eval abmask | C64_B4, abmask
.elseif $symcmp(reg,"B4") == 0
.eval abmask | C64_B4, abmask
.elseif $symcmp(reg,"b5") == 0
.eval abmask | C64_B5, abmask
.elseif $symcmp(reg,"B5") == 0
.eval abmask | C64_B5, abmask
.elseif $symcmp(reg,"b6") == 0
.eval abmask | C64_B6, abmask
.elseif $symcmp(reg,"B6") == 0
.eval abmask | C64_B6, abmask
.elseif $symcmp(reg,"b7") == 0
.eval abmask | C64_B7, abmask
.elseif $symcmp(reg,"B7") == 0
.eval abmask | C64_B7, abmask
.elseif $symcmp(reg,"b8") == 0
.eval abmask | C64_B8, abmask
.elseif $symcmp(reg,"B8") == 0
.eval abmask | C64_B8, abmask
.elseif $symcmp(reg,"b9") == 0
.eval abmask | C64_B9, abmask
.elseif $symcmp(reg,"B9") == 0
.eval abmask | C64_B9, abmask
.elseif $symcmp(reg,"b10") == 0
.eval abmask | C64_B10, abmask
.elseif $symcmp(reg,"B10") == 0
.eval abmask | C64_B10, abmask
.elseif $symcmp(reg,"b11") == 0
.eval abmask | C64_B11, abmask
.elseif $symcmp(reg,"B11") == 0
.eval abmask | C64_B11, abmask
.elseif $symcmp(reg,"b12") == 0
.eval abmask | C64_B12, abmask
.elseif $symcmp(reg,"B12") == 0
.eval abmask | C64_B12, abmask
.elseif $symcmp(reg,"b13") == 0
.eval abmask | C64_B13, abmask
.elseif $symcmp(reg,"B13") == 0
.eval abmask | C64_B13, abmask
.elseif $symcmp(reg,"b14") == 0
.eval abmask | C64_B14, abmask
.elseif $symcmp(reg,"B14") == 0
.eval abmask | C64_B14, abmask
.elseif $symcmp(reg,"b15") == 0
.eval abmask | C64_B15, abmask
.elseif $symcmp(reg,"B15") == 0
.eval abmask | C64_B15, abmask
.elseif $symcmp(reg,"amr") == 0 ; control registers
.eval cmask | C64_AMR, cmask
.elseif $symcmp(reg,"AMR") == 0
.eval cmask | C64_AMR, cmask
.elseif $symcmp(reg,"csr") == 0
.eval cmask | C64_CSR, cmask
.elseif $symcmp(reg,"CSR") == 0
.eval cmask | C64_CSR, cmask
.elseif $symcmp(reg,"ier") == 0
.eval cmask | C64_IER, cmask
.elseif $symcmp(reg,"IER") == 0
.eval cmask | C64_IER, cmask
.elseif $symcmp(reg,"ist") == 0
.eval cmask | C64_IST, cmask
.elseif $symcmp(reg,"IST") == 0
.eval cmask | C64_IST, cmask
.elseif $symcmp(reg,"irp") == 0
.eval cmask | C64_IRP, cmask
.elseif $symcmp(reg,"IRP") == 0
.eval cmask | C64_IRP, cmask
.elseif $symcmp(reg,"nrp") == 0
.eval cmask | C64_NRP, cmask
.elseif $symcmp(reg,"NRP") == 0
.eval cmask | C64_NRP, cmask
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